This week, developers with the Open Graphics Project are announcing that we have the PCB schematic for the OGD1 product ready for public review.

The Open Graphics Project is dedicated to developing open-architecture graphics hardware, specifically for use with Free and Open Source operating systems. Based on community feedback, we have defined a graphics architecture, and are working steadily towards producing real graphics hardware that "just works" with Linux, BSD, and other free operating systems.

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The first major step towards producing consumer graphics products is our "development platform" that we call OGD1. This product is not a graphics card. Rather, it is an FPGA-based project board, with memory and video hardware on it. It can be programmed to be a graphics card. Being FPGA-based, it is also useful for many things beyond just graphics and the needs of the OGP. We are selling this as a product because there is a market demand for FPGA-based prototyping boards, volunteers working with the OGP will need it for development, and we need a source of revenue to fund further development. Ultimately, we need to raise over $2 million to cover the cost of ASIC production alone.

The first phase of OGD1's PCB development is the "schematic." The schematic diagram defines only the logical connections between components on the board; pins on chips are identified, and the connections between them are defined, largely independent of physical constraints. This is distinct from "artwork," which defines the physical layout and trace routing; there, we define real, physical positions and orientations of chips, along with how traces are laid out in the different layers of the board. The correctness of the schematic is a necessary (but not sufficient) condition for the correctness of the artwork. We need members of the community to download and review the schematic so that we can more quickly find flaws and correct them. The artwork phase has already been started, with most component positioning completed. Corrections will be made as they are brought to our attention.

Designing OGD1 has required many compromises. We believe we have added every feature that was practical to do from an engineering standpoint. If we've forgotten something critical, please let us know. But our primary need is for community members to help us critique the correctness of the design, given the feature-set we have defined in the schematic.

An abridged list of features:

• 64-bit PCI (66MHz)/PCI-X (133MHz) interface
• 55K Look-Up-Table FPGA
• 256 megabytes of RAM
• Two Dual-link DVI-I outputs (two 330 MP/sec digital, one 330 MP/sec analog, one unpopulated 500 MP/sec analog)
• TV out (PAL, NTSC, SECAM)
• 96 user I/O

Short term schedule:

• Schematic - Finished
• Artwork - another 12 to 16 weeks
• Fabrication - another 4 weeks
• First populated boards - another 1 week

Ordering
We plan to start taking pre-orders as soon as possible, and will take regular orders as soon as the first populated boards are finished. We have a provider and a domain name for our upcoming website, but we've been putting all available time toward board design, not website design. If anyone in the community is interested in helping us design a nice website, feel free to join our mailing list to get involved in the project in that way. Final pricing of the boards is still being determined.

Links:

• Open Graphics Project Wiki [Lots of out of date info]
• Open Graphics Mailing List [Lots of out of date info]
• Schematic in PDF format

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Editorial comment: I'm including the announcement that was posted to the Open Graphics Project's mailing list, as it includes additional details. -Jeremy

From: Timothy Miller [email blocked]
To: open-graphics [email blocked]
Subject: ANNOUNCEMENT: Traversal to release OGD1 PCB schematic for public review
Date: Tue Feb 28 08:17:56 EST 2006

Within the next couple of days, we would like to publish the schematic
for OGD1 for public review.  It is ready now, but we need to figure
out exactly HOW and WHERE it should be posted.  We need to decide what
kind of file format is best to publish so that (a) it is convenient
and cheap for us to produce it and (b) as many people as possible are
able to view and evaluate it.  We need you to tell us how to handle
this.  The main obstacle is that we've been using Veribest to do the
work.

The official location for the ensuing discussion is the Open Graphics
Project main mailing list. 
(http://lists.duskglow.com/mailman/listinfo/open-graphics)

Although we will pay attention to private emails, I reserve the right
to break netiquette (I'm warning you in advance) and forward some
comments to the list.  Mostly, this is to deal with the fact that
people sometimes forget to CC the list when they meant to, and I don't
want to waste a lot of time asking permission.  If you want to comment
on this privately and absolutely do not want me to forward it to the
list, tell me explicitly, and I'll honor that.

What we have discussed on this list and what Howard and Andy have done
have not always been in perfect alignment.  Naturally, they have paid
attention to requirements I have sent them, but they have also had to
make engineering decisions of their own that may have consequences for
the rest of us.  That is the nature of engineering, and they have done
the best job they can under the circumstances.

The feature set of the design being presented for review is
essentially etched in stone.  While it's possible that we may modify
the design to add a feature that was a moronic oversight on our part,
for the most part what we need is for people to check the CORRECTNESS
of the design.  It should be obvious from the schematic what our
feature set and goals are.  Are those achieved?  Have we made
mistakes?  Is there something we can do to minimize potential
problems?  You get the idea.

Compared to earlier discussions, here are some design changes you may notice:

* We have switched our main FPGA from Xilinx to Lattice.  Compared to
the Xilinx 3S4000, the Lattice ECP2-50 has more logic area, is less
expensive, and the synthesis tools are free of charge.  Unfortunately,
it has about 1/3 fewer usable I/O pins, but we've dealt with that as
best we can.
* Primary "user I/O" bus from the main FPGA is 66 pins.  Another set
comes from pin banks whose reference voltages may or may not make them
useful to you.  Another set comes from unused pins on the Lattice
XP10.  Additional ones can be connected to unpopulated pads for
optional parts.
* The "local bus" interface between the XP10 and the main FPGA had to
be reduced in pin count.  The result is that we will need to use a bit
more logic to multiplex traffic across this bus at a higher data rate.
 Some of those signals are connected to pins on the main FPGA where
the PCB routing will be suboptimal; as a result, those signals will
have to work at a lower clock rate.
* The PCI card edge has been extended to the full 64 bits and can be
configured to indicate to the host that it supports PCI-X (133 Mhz). 
(The RTL code we develop for OGA may or may not support the extended
bus width.)

The licensing of this IP is largely unchanged, but here are the details:

* The IP being licensed here refers to schematics, artwork, and other
information necessary to reproduce the OGD1 blank printed circuit
board.  Additional IP that may be necessary for manufacturing a fully
functional device (such as bitfiles and firmware) is not covered here.
* Traversal retains copyright of this design and has the right to
privately and publicly license it any way they see fit, as well as
produce derivative works without restriction, license others to have
similar rights, etc.
* This design is being released to the community under the GPL
license.  As soon as the first board is sold based on this PCB design,
the public license will automatically change to LGPL.
* By default, Traversal reserves the right to adopt into their
privately licensable IP any changes or modifications offered by the
community to the OGP, Traversal, or an agent of either.  All such
changes will also be released under (L)GPL immediately.  Trademarks
associated with Traversal Technology and the Open Graphics Project are
barred from any other use of this IP.

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Related Links:

• Archive of above thread