On Fri, Jun 04, 2010 at 07:44:21PM +0300, Dexter Tomisson wrote:
quoted text
> On 4 June 2010 14:25, Andreas Gerdd <kryptosnet@gmail.com> wrote:
> 
> > And should we expect having a better support for Intel Core i5/i7 CPUs
> > in the near future, maybe for the next release cycle?
> >
> >
> >
> Sounds no;
> 
> Changes by:
> 
> 	jsg@cvs.openbsd.org
> 
> 	2010/06/04 09:03:35
> Modified files:
> 
> 	sys/arch/amd64/amd64: est.c
> 
> 	sys/arch/i386/i386: machdep.c
> Log message:
> Don't warn about not knowing what the bus clock is on core i7/i5/i3
> as the high/low guessing won't be done on these processors due to MSR
> differences.
> 
> Just 'hide' them. Such a great solution!

Look at the code, look at the MSRs, take FSB_FREQ for example,
this is not valid on nehalem (no FSB).  Take the interpretation
of PERF_STATUS using bits that Intel claims are reserved.

The ACPI and non ACPI codepaths need to be more isolated
from each other and this then needs to be heavily tested.

If you were to invest just the smallest of amounts of time
looking at how it actually works and the history of the
speedstep code you'd understand.