After doing some basic testing and debugging, I decided to start
taking a crack at optimizing the memory controller for speed.

Here's the longest combinatorial path right now:

Slack:                  -5.272ns (requirement - (data path - clock
path skew + uncertainty))
  Source:               cmd_i_0 (FF)
  Destination:          cs/last_row_0_10 (FF)
  Requirement:          5.000ns
  Data Path Delay:      9.907ns (Levels of Logic = 3)
  Clock Path Skew:      -0.365ns
  Source Clock:         clock_BUFGP rising at 0.000ns
  Destination Clock:    clock_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Data Path: cmd_i_0 to cs/last_row_0_10
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    AA16.IQ1             Tiockiq               0.259   cmd_in<0>
                                                       cmd_i_0
    SLICE_X106Y46.G3     net (fanout=2)        3.441   cmd_i<0>
    SLICE_X106Y46.Y      Tilo                  0.608   N1733
                                                       bf/cmd_out<0>1
    SLICE_X118Y44.G2     net (fanout=10)       1.863   cmd_buf2cs<0>
    SLICE_X118Y44.Y      Tilo                  0.608   cs/_n0072
                                                       cs/_n00721
    SLICE_X119Y41.G3     net (fanout=4)        0.428   cs/N11
    SLICE_X119Y41.Y      Tilo                  0.551   cs/_n0068
                                                       cs/_n00682
    SLICE_X117Y36.CE     net (fanout=7)        1.547   cs/_n0068
    SLICE_X117Y36.CLK    Tceck                 0.602   cs/last_row_0_11
                                                       cs/last_row_0_10
    -------------------------------------------------
---------------------------
    Total                                      9.907ns (2.628ns logic,
7.279ns route)
                                                       (26.5% logic,
73.5% route)

I'm not sure that I need any help.  I just thought some might want to
watch as the design evolves.  But suggestions are definitely welcome.

The tool currently is set to put registers into input and output
buffers.  Signals that would normally be internal to the design are
I/O pins, because the only thing I'm synthesizing is the memory
controller.  Thus, I have isolate some of the signals using an extra
layer of registers.

The path here goes from the command into the controller to the
register that stores the last memory row for each bank.
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