> On Monday 17 April 2006 23:04, Nicolas Boulay wrote:
quoted text
>> Le samedi 15 Avril 2006 17:27, Lourens Veen a écrit :
>> > Newer processors can simply have more
>> > functional units, and could be backwards compatible with their
>> > predecessors.
>>
>> One of the backside of MISC is that you can't be backwards
>> compatible. You needs more space to define new register. You need to
>> define different latency. Basicaly the instruction world look like a
>> 2 registers, one read, one write. You could add a bit to the input
>> register for immediat numbers. If you use 64 registers, it take 6
>> bits.
>
> You are right, I hadn't thought of that. If there were room for
> extensibility in the opcode format, and you didn't improve upon the
> functional units themselves, it could be made backward compatible, but
> as you say, it's not necessary.

If you keep room for few more adresse, you waste memory for the code. And
you save half of the problem. If you make a vliw design, you could pass
from 4 to 8 instructions in the same word but if you really do 4
instructions, you add some constraints that make the design less
competitive.

quoted text
>
> Lourens
>


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