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MI interrupt description

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[view original message]
From: Joerg Sonnenberger <joerg@...>
To: <tech-kern@...>
Subject: MI interrupt description
Date: Thursday, October 4, 2007 - 2:23 pm

Hi all,

is it possible to define platform independent definitions for normal

interrupt routing constants? From x86 we have to distinguish at least

between Active Low / Active High and Edge / Level triggered interrupts.


I want to push this into the IOAPIC and i8259 handling on x86 at some

point as the current code is a mess abusing the IOAPIC constants in many

places, so I would like to see if we can come up with a generic list.


Joerg
[view original message]
From: Tim Rightnour <root@...>
To: Joerg Sonnenberger <joerg@...>
Cc: <tech-kern@...>
Subject: RE: MI interrupt description
Date: Saturday, October 6, 2007 - 11:34 am

On prep we only really need edge and level, however, we also have positive and

negative polarity on them, and in a few minor nit cases we do have to care

about those.


There is also supposedly a pulse type out there, but none of the ppc ports I

know of use it..  might be for some other type of hardware?


---

Tim Rightnour <root@garbled.net>

NetBSD: Free multi-architecture OS http://www.netbsd.org/

Genecys: Open Source 3D MMORPG: http://www.genecys.org/
[view original message]
From: David Laight <david@...>
To: <tech-kern@...>
Subject: Re: MI interrupt description
Date: Thursday, October 4, 2007 - 3:57 pm

If you want to do this generically, you need to allow for interrupts

to be triggered on either the rising, falling or both edges.


In the past I've had to pass the level/edge info in the high bits of the

priority field in order to save device drivers having to know the

gory details of interrupt routing (that was an SA1100/1101 system running

an OS I never want to have to handle again).


	David


--

David Laight: david@l8s.co.uk
[view original message]
From: Joerg Sonnenberger <joerg@...>
To: <tech-kern@...>
Subject: Re: MI interrupt description
Date: Thursday, October 4, 2007 - 4:20 pm

Do we have any cases for the third? Active High and Active Low are the

other two cases. I don't think this is exposed to normal drivers, just

bus drivers and PICs.


Joerg
[view original message]
From: Michael Lorenz <macallan@...>
To: Joerg Sonnenberger <joerg@...>
Cc: <tech-kern@...>
Subject: Re: MI interrupt description
Date: Thursday, October 4, 2007 - 3:08 pm

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Hello,


macppc distinguishes only between edge and level triggered.

While there - what about IPLs ?


have fun

Michael

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[view original message]
From: Joerg Sonnenberger <joerg@...>
To: <tech-kern@...>
Subject: Re: MI interrupt description
Date: Thursday, October 4, 2007 - 3:11 pm

I'm mostly concerned about the information needed for PIC programming.

The IPL handling is independent of that.


Joerg
Previous thread: ACPI Error (psparse-0626) by C. K. on Thursday, October 4, 2007 - 10:08 am. (2 messages)

Next thread: Thread benchmarks, round 2 by Andrew Doran on Thursday, October 4, 2007 - 7:04 pm. (14 messages)