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MI interrupt description

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From: Joerg Sonnenberger <joerg@...>
To: <tech-kern@...>
Subject: MI interrupt description
Date: Thursday, October 4, 2007 - 2:23 pm

Hi all,
is it possible to define platform independent definitions for normal
interrupt routing constants? From x86 we have to distinguish at least
between Active Low / Active High and Edge / Level triggered interrupts.

I want to push this into the IOAPIC and i8259 handling on x86 at some
point as the current code is a mess abusing the IOAPIC constants in many
places, so I would like to see if we can come up with a generic list.

Joerg
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Messages in current thread:
MI interrupt description, Joerg Sonnenberger, (Thu Oct 4, 2:23 pm)
RE: MI interrupt description, Tim Rightnour, (Sat Oct 6, 11:34 am)
Re: MI interrupt description, David Laight, (Thu Oct 4, 3:57 pm)
Re: MI interrupt description, Joerg Sonnenberger, (Thu Oct 4, 4:20 pm)
Re: MI interrupt description, Michael Lorenz, (Thu Oct 4, 3:08 pm)
Re: MI interrupt description, Joerg Sonnenberger, (Thu Oct 4, 3:11 pm)