Sorry, I dont get it. You are referring to softirqs, while I speak
of hardware (NIC) interrupts, that can be masked for ever.
With your patch :
CPU0 CPU1
napi_complete();
/* please note there is no smp_wmb()
in __napi_complete() after
clear_bit(NAPI_STATE_SCHED, &n->state);
(It's implied on x86 because of lock prefix)
*/
writel(np->irqmask, base + NvRegIrqMask)
writel(0, base + NvRegIrqMask);
napi_schedule(&np->napi); // might do nothing because this cpu see
// NAPI_STATE_SCHED set to one
NIC cannot deliver further interrupts.
With my patch :
CPU0 CPU1
napi_complete();
/* please note there is no smp_wmb()
in __napi_complete() after
clear_bit(NAPI_STATE_SCHED, &n->state);
*/
writel(np->irqmask, base + NvRegIrqMask)
if (napi_schedule_prep(&np->napi)) // if false, NIC can deliver further interrupts.
// if true, we mask interrupts but re-enable napi. packets will be processed,
// interrupt will be re-enabled later.
My patch has a guarantee that we mask NIC interrupts *only* if napi is re-scheduled.
It probably makes no difference on x86, but it might be better to have same logic in all drivers...
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