On Wed, Jul 01, 2009 at 06:58:52PM +0800, Herbert Xu wrote:I take that back. Andi, please look at section 8.2.3.4 of the IA-32 Architectures Software Developer's Manual Volume 3A, "Loads May Be Reordered with Earlier Stores to Different Locations. This seems to be exactly the scenario that we have here, and shows why mfence is required. In our case, we're doing CPU1 CPU2 Write data ready Add ourselves to wait queue Read wait queue to notify Check data ready Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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