On Tue, 2009-03-17 at 15:09 -0700, Bernhard Schmidt wrote:
Thanks for the information. The memory enable bit in the PCI command
register was cleared during tx_timeout. That's why all the registers
were reading 0xffffffff. The tx_timeout code in tg3 would not be able
to reset the chip if that bit was cleared. We need to find out why that
bit was cleared. We should also enhance the tx timeout code so that it
can recover more completely even if the memory enable bit is cleared.
Thanks.
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