Benjamin Herrenschmidt wrote:
quoted text
> On Tue, 2009-03-10 at 21:50 +0200, Felix Radensky wrote:
>   
>> Hi,
>>
>> I'm experiencing RX problem on custom board based on AMCC
>> 405EXr processor. Channel 0 of EMAC is connected to 10/100
>> Micrel KSZ8041NL PHY in MII mode. Ethernet works fine in
>> u-boot (version 2009.01). In Linux (2.6.27) Ethernet works fine
>> as well if EMAC was initialized in u-boot. It is enough to send
>> ping from u-boot (even to non-existing host) to make things work
>> in linux. But if u-boot takes kernel and ramdisk images from flash
>> and does not initialize EMAC only TX side works in linux.
>>     
>
> You should CC linuxppc-dev where you are more likely to find people to
> help here.
>
>   

I've sent a message to linuxppc-dev yesterday, but didn't get any reply 
so far.
quoted text
>> I can see that TX counters are incremented when pinging from
>> EMAC side, but RX counters remain zero.  RX error counter
>> in PHY is zero as well.  I've enabled debugging in EMAC
>> driver and verified that RX EOB interrupt is not triggered.
>> FER register in RGMII bridge is properly configured for MII
>> mode on channel 0.  I've tried to dump EMAC registers using
>> ethtool and got machine check exception.
>>
>> I don't know what else could be done to identify the source of
>> the problem. Any tips would be greatly appreciated.
>>     
>
> I don't have a 405EXr here, but it smells like the old reset problem
> when the link is down. Maybe we are missing code to force clocks on
> 405EXr when there's no link ?
>   

Yes, seems logical. U-boot has code to enable and disable loopback clock
for 440SPE, 440EPX,440GRX,405EX, 460EX and 460GT.

I can test patches on my board. Alternatively, I can try something myself
if you can provide some guidance. I guess you are referring to the code 
using
EMAC_FTR_440GX_PHY_CLK_FIX and EMAC_FTR_440EP_PHY_CLK_FIX.

Thanks.

Felix.

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