Hi Dave, Roland,

I'm submitting 2 patches against cxgb3 and iw_cxgb3 respectively.
They are built against net-next-2.6.
The first patch adds a notification mechanism to cxgb3 to alert
the upper layer drivers (iWARP and iSCSI) of a chip reset.

The second patch adds the handler for such an event in the iWARP driver.

Since the second patch depends on the first one, I submit them together,
even though the second patch should be submitted against Roland's tree.

Cheers,
Divy

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> I'm submitting 2 patches against cxgb3 and iw_cxgb3 respectively.
 > They are built against net-next-2.6.
 > The first patch adds a notification mechanism to cxgb3 to alert
 > the upper layer drivers (iWARP and iSCSI) of a chip reset.
 > 
 > The second patch adds the handler for such an event in the iWARP driver.
 > 
 > Since the second patch depends on the first one, I submit them together,
 > even though the second patch should be submitted against Roland's tree.

simplest thing is for Dave to merge both, and I'm fine with that.

 - R.
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From: Roland Dreier <rdreier@cisco.com>

Ok, I'll take care of this.
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Hello

Some lspci:
lspci
00:00.0 Host bridge: Intel Corporation Memory Controller Hub (rev 90)
00:02.0 PCI bridge: Intel Corporation PCI Express x8 Port 2-3 (rev 90)
00:04.0 PCI bridge: Intel Corporation PCI Express x16 Port 4-7 (rev 90)
00:08.0 System peripheral: Intel Corporation DMA Engine (rev 90)
00:10.0 Host bridge: Intel Corporation FSB Registers (rev 90)
00:10.1 Host bridge: Intel Corporation FSB Registers (rev 90)
00:10.2 Host bridge: Intel Corporation FSB Registers (rev 90)
00:11.0 Host bridge: Intel Corporation Reserved Registers (rev 90)
00:13.0 Host bridge: Intel Corporation Reserved Registers (rev 90)
00:15.0 Host bridge: Intel Corporation DDR Channel 0 Registers (rev 90)
00:16.0 Host bridge: Intel Corporation DDR Channel 1 Registers (rev 90)
00:1a.0 USB Controller: Intel Corporation USB UHCI Controller #4 (rev 02)
00:1a.7 USB Controller: Intel Corporation USB2 EHCI Controller #2 (rev 02)
00:1c.0 PCI bridge: Intel Corporation PCI Express Port 1 (rev 02)
00:1c.4 PCI bridge: Intel Corporation PCI Express Port 5 (rev 02)
00:1c.5 PCI bridge: Intel Corporation PCI Express Port 6 (rev 02)
00:1d.0 USB Controller: Intel Corporation USB UHCI Controller #1 (rev 02)
00:1d.1 USB Controller: Intel Corporation USB UHCI Controller #2 (rev 02)
00:1d.2 USB Controller: Intel Corporation USB UHCI Controller #3 (rev 02)
00:1d.7 USB Controller: Intel Corporation USB2 EHCI Controller #1 (rev 02)
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92)
00:1f.0 ISA bridge: Intel Corporation LPC Interface Controller (rev 02)
00:1f.2 IDE interface: Intel Corporation 4 port SATA IDE Controller (rev 02)
00:1f.3 SMBus: Intel Corporation SMBus Controller (rev 02)
00:1f.5 IDE interface: Intel Corporation 2 port SATA IDE Controller (rev 02)
01:00.0 Ethernet controller: Intel Corporation Device 10dd (rev 01)
04:00.0 Ethernet controller: Intel Corporation 82573E Gigabit Ethernet 
Controller (Copper) (rev 03)
05:00.0 Ethernet controller: Intel Corporation 82573L Gigabit Ethernet ...
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See above in dmesg: It's disabled in BIOS. If the BIOS doesn't have an
option to enable DCA, you need to talk to your vendor. Or you can try
changing registers on the chipset manually...

Brice

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yes ok.
but in bios i have an option to enable DCA and i make it. (so DCA is 
enabled in bios )

thats why i ask question why is not enabled :)

So i think only changing registers may help ...

Thanks for reply.

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Forwarding entire message to include e1000-devel


Probably because the BIOS is not working correctly or there is a bug in 
dca. Is that a supermicro machine?  Can you include the output of 
dmidecode?  Are you running the latest BIOS?  What are you trying to 

The DMA channels (copy offload) are different than the DCA feature.  DCA 
involves front side bus hints sent from the adapter to the CPU handling 
the interrupt, where DMA channels are for copy offload from the processor 
to the independent data movers (DMA channels)

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Yes this is an supermicro board X7DCT-10G
http://www.supermicro.com/products/motherboard/Xeon1333/5100/X7DCT-10G.cfm
Bios is no latest but in new bios is no info in changelog about ioat/dca 
so i don't update
i want to test / compare DCA over IOAT with my env that is Traffic 
management Linux sever
with more than 3Gbit/s traffic and 10k users.


dmidecode:
# dmidecode 2.9
SMBIOS 2.5 present.
39 structures occupying 1950 bytes.
Table at 0xDFF5F000.

Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
        Vendor: Phoenix Technologies LTD
        Version: 1.0c
        Release Date: 07/10/2008
        Address: 0xE5100
        Runtime Size: 110336 bytes
        ROM Size: 2048 kB
        Characteristics:
                ISA is supported
                PCI is supported
                PNP is supported
                BIOS is upgradeable
                BIOS shadowing is allowed
                ESCD support is available
                Boot from CD is supported
                Selectable boot is supported
                BIOS ROM is socketed
                EDD is supported
                5.25"/1.2 MB floppy services are supported (int 13h)
                3.5"/720 KB floppy services are supported (int 13h)
                3.5"/2.88 MB floppy services are supported (int 13h)
                Print screen service is supported (int 5h)
                8042 keyboard services are supported (int 9h)
                Serial services are supported (int 14h)
                Printer services are supported (int 17h)
                CGA/mono video services are supported (int 10h)
                ACPI is supported
                USB legacy is supported
                BIOS boot specification is supported
                Targeted content distribution is supported

Handle 0x0001, DMI type 1, 27 bytes
System Information
        Manufacturer: Supermicro
        Product Name: X7DCT
        Version: 0123456789
        Serial Number: 0123456789
        UUID: ...
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