From: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Date: Mon, 19 Jan 2009 16:11:05 -0800

quoted text
> The is an issue where setting Relaxed Ordering (RO) bit
> (in a PCI-E write transaction) on 82598 causing the chipset
> to drop DCA hints.  This patch forces RO not to be set for
> descriptors as well as payload.  This will only be in effect
> while DCA is enabled and no performance difference was
> noticed in testing.
> 
> Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
> Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

Applied.
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