Re: Mask bit support's API

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From: Yang, Sheng
Date: Tuesday, November 23, 2010 - 6:59 pm

On Tuesday 23 November 2010 22:06:20 Avi Kivity wrote:

Of course KVM should service reading from pending bitmask. For assigned device, 
it's kernel who would set the pending bit; but I am not sure for virtio. This 
interface is GET_ENTRY, so reading is fine with it.
 

In fact modifying irq routing in the kernel is also the thing I want to avoid.

So, the flow would be:

kernel get MMIO write, record it in it's own MSI table
KVM exit to QEmu, by one specific exit reason
QEmu know it have to sync the MSI table, then reading the entries from kernel
QEmu found it's an write, so it need to reprogram irq routing table using the 
entries above
done

But wait, why should qemu read entries from kernel? By default exit we already 
have the information about what's the entry to modify and what to write, so we can 
use them directly. By this way, we also don't need an specific exit reason - just 
exit to qemu in normal way is fine.

Then it would be:

kernel get MMIO write, record it in it's own MSI table
KVM exit to QEmu, indicate MMIO exit
QEmu found it's an write, it would update it's own MSI table(may need to query 
mask bit from kernel), and reprogram irq routing table using the entries above
done

Then why should kernel kept it's own MSI table? I think the only reason is we can 
speed up reading in that way - but the reading we want to speed up is mostly on 
enabled entry(the first entry), which is already in the IRQ routing table... 

And for enabled/disabled entry, you can see it like this: for the entries inside 
routing table, we think it's enabled; otherwise it's disabled. Then you don't need 
to bothered by pci_enable_msix().

So our strategy for reading accelerating can be:

If the entry contained in irq routing table, then use it; otherwise let qemu deal 
with it. Because it's the QEmu who owned irq routing table, the synchronization is 
guaranteed. We don't need the MSI table in the kernel then.

And for writing, we just want to cover all of mask bit, but none of others.

I think the concept here is more acceptable?

The issue here is MSI table and irq routing table got duplicate information on 
some entries. My initial purposal is to use irq routing table in kernel, then we 
don't need to duplicate information.


--
regards
Yang, Sheng
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Messages in current thread:
Mask bit support's API, Yang, Sheng, (Mon Nov 22, 11:09 pm)
Re: Mask bit support's API, Avi Kivity, (Mon Nov 22, 11:17 pm)
Re: Mask bit support's API, Yang, Sheng, (Mon Nov 22, 11:35 pm)
Re: Mask bit support's API, Avi Kivity, (Tue Nov 23, 12:54 am)
Re: Mask bit support's API, Yang, Sheng, (Tue Nov 23, 1:30 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Tue Nov 23, 5:04 am)
Re: Mask bit support's API, Avi Kivity, (Tue Nov 23, 5:47 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Tue Nov 23, 5:56 am)
Re: Mask bit support's API, Yang, Sheng, (Tue Nov 23, 6:57 am)
Re: Mask bit support's API, Yang, Sheng, (Tue Nov 23, 7:02 am)
Re: Mask bit support's API, Avi Kivity, (Tue Nov 23, 7:06 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Tue Nov 23, 8:11 am)
Re: Mask bit support's API, Gleb Natapov, (Tue Nov 23, 8:24 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Tue Nov 23, 9:10 am)
Re: Mask bit support's API, Yang, Sheng, (Tue Nov 23, 6:59 pm)
Re: Mask bit support's API, Yang, Sheng, (Thu Nov 25, 7:35 pm)
Re: Mask bit support's API, Avi Kivity, (Tue Nov 30, 7:15 am)
Re: Mask bit support's API, Yang, Sheng, (Tue Nov 30, 7:36 pm)
Re: Mask bit support's API, Avi Kivity, (Thu Dec 2, 6:09 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Thu Dec 2, 6:47 am)
Re: Mask bit support's API, Avi Kivity, (Thu Dec 2, 6:56 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Thu Dec 2, 7:26 am)
Re: Mask bit support's API, Sheng Yang, (Thu Dec 2, 7:54 am)
Re: Mask bit support's API, Michael S. Tsirkin, (Thu Dec 2, 9:55 am)
Re: Mask bit support's API, Yang, Sheng, (Thu Dec 2, 8:03 pm)