On Mon, 2011-01-03 at 12:39 -0800, David Miller wrote:
OK.
# lspci -vvxx -s 0:0:03
0000:00:03.0 VGA compatible controller: S3 Inc. ViRGE/DX or /GX (rev 01)
(prog-if 00 [VGA controller])
Subsystem: S3 Inc. ViRGE/DX
Physical Slot: PCI 3
Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop-
ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
<TAbort- <MAbort- >SERR- <PERR- INTx-
Interrupt: pin A routed to IRQ 23
Region 0: Memory at 14000000 (32-bit, non-prefetchable)
[size=64M]
Region 1: [virtual] Memory at fffff80200000000 (32-bit,
non-prefetchable) [size=1]
Region 2: [virtual] Memory at fffff80200000000 (32-bit,
non-prefetchable) [size=1]
Region 3: [virtual] Memory at fffff80200000000 (32-bit,
non-prefetchable) [size=1]
Region 4: [virtual] Memory at fffff80200000000 (32-bit,
non-prefetchable) [size=1]
Region 5: [virtual] Memory at fffff80200000000 (32-bit,
non-prefetchable) [size=1]
Expansion ROM at 00130000 [disabled] [size=64K]
Kernel driver in use: s3fb
Kernel modules: s3fb
00: 33 53 01 8a 02 00 00 02 01 00 00 03 00 40 00 00
10: 00 00 00 14 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 33 53 01 8a
30: 00 00 13 00 00 00 00 00 00 00 00 00 00 01 04 ff
Those are 32 bit addresses, so I suppose I should be getting the base
address for the registers accesses from region 1, right?
--
Tactical Nuclear Kittens
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