On Thu, Sep 30, 2010 at 06:39:45PM +0100, Matthew Garrett wrote:
quoted text
> On Thu, Sep 30, 2010 at 11:38:28AM -0400, Matthew Garrett wrote:
> > AMD's reference BIOS code had a bug that could result in the firmware
> > failing to reenable the iommu on resume. It transpires that this causes
> > certain less than desirable behaviour when it comes to PCI accesses, to
> > whit them ending up somewhere near Bristol when the more desirable outcome
> > was Edinburgh. Sadness ensues, perhaps along with filesystem corruption.
> > Let's make sure that it gets turned back on.
> 
> Of course, this isn't actually sufficient - nothing in the iommu code 
> appears to reprogram the BAR, for instance. Joerg, how is this meant to 
> work?

Enabling the IOMMU device is only part of what the BIOS is supposed to
do to get the IOMMU ready for the OS. A handful of registers in the
config space of the device and the IOMMU MMIO region must also be
restored. Thats the simple part. The IOMMU device also spans two
indirect register spaces to configure the IOMMU caches. I have no idea
yet how this need to be configured. The plan is definitly to
work-around a missing IOMMU device in the IOMMU driver. But I am still
talking to some people to find out what exactly must be done, especially
with the indirect register spaces.


	Joerg


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