From: Andreas Herrmann <andreas.herrmann3@amd.com>

So far we only provide num_k8_northbridges. This is required in
different areas (e.g. L3 cache index disable, GART). But not all AMD
CPUs provide a GART. Thus it is useful to split off the GART handling
from the generic caching of AMD northbridge misc devices.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/include/asm/k8.h             |   13 +++++---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    4 +-
 arch/x86/kernel/k8.c                  |   52 +++++++++++++++++++--------------
 arch/x86/kernel/pci-gart_64.c         |   27 +++++++++++------
 drivers/char/agp/amd64-agp.c          |   33 ++++++++++++++------
 drivers/edac/amd64_edac.c             |    2 +-
 6 files changed, 82 insertions(+), 49 deletions(-)


Please apply.


Thanks,

Andreas


diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index af00bd1..9cee145 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -7,24 +7,27 @@ extern struct pci_device_id k8_nb_ids[];
 struct bootnode;
 
 extern int early_is_k8_nb(u32 value);
-extern struct pci_dev **k8_northbridges;
-extern int num_k8_northbridges;
 extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
 extern int k8_get_nodes(struct bootnode *nodes);
 extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
 extern int k8_scan_nodes(void);
 
+struct k8_northbridge_info {
+	u16 num;
+	u8 gart_supported;
+	struct pci_dev **nb_misc;
+};
+extern struct k8_northbridge_info k8_northbridges;
+
 #ifdef CONFIG_K8_NB
-extern int num_k8_northbridges;
 
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
-	return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
+	return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
 }
 
 #else
-#define num_k8_northbridges 0
 
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
diff --git ...
[ message continues ]

From just looking at it: isn't this patch going to break compiling with
CONFIG_K8_NB=n?

	-hpa


-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

--

[ message continues ]

Good catch.

Compiled for me after deselecting CONFIG_CPU_SUP_AMD but deselecting
PCI breaks compilation of the L3 cache index disable code. But that
stuff requires PCI support.

Will send updated patch(es) to fix this.


Thanks,

Andreas

--

[ message continues ]

Following patches are against tip/master as of
v2.6.36-rc3-1233-gf3d0a67

Patch 1 sets the correct dependency to K8_NB for L3 cache index disable code
Patch 2 allows separate handling of gart and AMD northbridges
Patch 3 renames k8.[ch] and CONFIG_K8_NB to the more appropriate amd_nb.[ch] and CONFIG_AMD_NB

Please apply.


Thanks,
Andreas
--

[ message continues ]

From: Andreas Herrmann <andreas.herrmann3@amd.com>

L3 cache index disable code uses PCI accesses to AMD northbridge functions.
Currently the code is compiled #ifdef CONFIG_CPU_SUP_AMD.
But its real dependency is #if (defined(CONFIG_CPU_SUP_AMD) &&
defined(CONFIG_PCI)) which in the end is a dependency to CONFIG_K8_NB.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 898c2f4..2521cdc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -306,7 +306,7 @@ struct _cache_attr {
 	ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
 };
 
-#ifdef CONFIG_CPU_SUP_AMD
+#ifdef CONFIG_K8_NB
 
 /*
  * L3 cache descriptors
@@ -556,12 +556,12 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
 		show_cache_disable_1, store_cache_disable_1);
 
-#else	/* CONFIG_CPU_SUP_AMD */
+#else	/* CONFIG_K8_NB */
 static void __cpuinit
 amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
 {
 };
-#endif /* CONFIG_CPU_SUP_AMD */
+#endif /* CONFIG_K8_NB */
 
 static int
 __cpuinit cpuid4_cache_lookup_regs(int index,
@@ -1000,7 +1000,7 @@ static struct attribute *default_attrs[] = {
 
 static struct attribute *default_l3_attrs[] = {
 	DEFAULT_SYSFS_CACHE_ATTRS,
-#ifdef CONFIG_CPU_SUP_AMD
+#ifdef CONFIG_K8_NB
 	&cache_disable_0.attr,
 	&cache_disable_1.attr,
 #endif
-- 
1.6.4.4

--

[ message continues ]

From: Andreas Herrmann <andreas.herrmann3@amd.com>

So far we only provide num_k8_northbridges. This is required in
different areas (e.g. L3 cache index disable, GART). But not all AMD
CPUs provide a GART. Thus it is useful to split off the GART handling
from the generic caching of AMD northbridge misc devices.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/include/asm/k8.h             |   13 +++++---
 arch/x86/kernel/cpu/intel_cacheinfo.c |    4 +-
 arch/x86/kernel/k8.c                  |   52 +++++++++++++++++++--------------
 arch/x86/kernel/pci-gart_64.c         |   27 +++++++++++------
 drivers/char/agp/amd64-agp.c          |   33 ++++++++++++++------
 drivers/edac/amd64_edac.c             |    2 +-
 6 files changed, 82 insertions(+), 49 deletions(-)

diff --git a/arch/x86/include/asm/k8.h b/arch/x86/include/asm/k8.h
index af00bd1..9cee145 100644
--- a/arch/x86/include/asm/k8.h
+++ b/arch/x86/include/asm/k8.h
@@ -7,24 +7,27 @@ extern struct pci_device_id k8_nb_ids[];
 struct bootnode;
 
 extern int early_is_k8_nb(u32 value);
-extern struct pci_dev **k8_northbridges;
-extern int num_k8_northbridges;
 extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
 extern int k8_get_nodes(struct bootnode *nodes);
 extern int k8_numa_init(unsigned long start_pfn, unsigned long end_pfn);
 extern int k8_scan_nodes(void);
 
+struct k8_northbridge_info {
+	u16 num;
+	u8 gart_supported;
+	struct pci_dev **nb_misc;
+};
+extern struct k8_northbridge_info k8_northbridges;
+
 #ifdef CONFIG_K8_NB
-extern int num_k8_northbridges;
 
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
-	return (node < num_k8_northbridges) ? k8_northbridges[node] : NULL;
+	return (node < k8_northbridges.num) ? k8_northbridges.nb_misc[node] : NULL;
 }
 
 #else
-#define num_k8_northbridges 0
 
 static inline struct pci_dev *node_to_k8_nb_misc(int node)
 {
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c ...
[ message continues ]

From: Andreas Herrmann <andreas.herrmann3@amd.com>

The file names are somehow misleading as the code is not specific to
AMD K8 CPUs anymore. The files accomodate code for other AMD CPU
northbridges as well.

Same is true for the config option which is valid for AMD CPU
northbridges in general and not specific to K8.

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
---
 arch/x86/Kconfig                      |    4 +-
 arch/x86/include/asm/amd_nb.h         |   39 +++++++++
 arch/x86/include/asm/k8.h             |   39 ---------
 arch/x86/kernel/Makefile              |    2 +-
 arch/x86/kernel/amd_nb.c              |  145 +++++++++++++++++++++++++++++++++
 arch/x86/kernel/aperture_64.c         |    2 +-
 arch/x86/kernel/cpu/intel_cacheinfo.c |   10 +-
 arch/x86/kernel/k8.c                  |  145 ---------------------------------
 arch/x86/kernel/pci-gart_64.c         |    2 +-
 arch/x86/kernel/setup.c               |    2 +-
 arch/x86/mm/k8topology_64.c           |    2 +-
 arch/x86/mm/numa_64.c                 |    2 +-
 drivers/char/agp/Kconfig              |    2 +-
 drivers/char/agp/amd64-agp.c          |    2 +-
 drivers/edac/Kconfig                  |    2 +-
 drivers/edac/amd64_edac.c             |    2 +-
 16 files changed, 201 insertions(+), 201 deletions(-)
 create mode 100644 arch/x86/include/asm/amd_nb.h
 delete mode 100644 arch/x86/include/asm/k8.h
 create mode 100644 arch/x86/kernel/amd_nb.c
 delete mode 100644 arch/x86/kernel/k8.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0c14369..308b9fb 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -640,7 +640,7 @@ config GART_IOMMU
 	bool "GART IOMMU support" if EMBEDDED
 	default y
 	select SWIOTLB
-	depends on X86_64 && PCI && K8_NB
+	depends on X86_64 && PCI && AMD_NB
 	---help---
 	  Support for full DMA access of devices with 32bit memory access only
 	  on systems with more than 3GB. This is usually needed for USB,
@@ -2055,7 +2055,7 @@ config OLPC_OPENFIRMWARE
 
 endif ...
[ message continues ]