If there are "zillions" that suggests the HW
engineers have version/naming issues just like
certain software engineers. Only goes to show
My suggestion was to use the name provided/used
by the hardware engineers. (E.g. whatever the
Verilog or VHDL equivalent of a module name is.)
So -- NO RENAME -- except for the driver.
If I understand you correctly, those engineers
are not reusing a named module; they are at best
just copying/pasting some Verilog/VHDL and adding
ASIC/SoC/.../FPGA-specific hacks. (Which calls into
question just how much assurance there can be that
Someone should have a few words with those hardware
engineers about module naming and consistency, so
software doesn't need to work around such issues.
Such problems have been solved for decades, and
there's no reason to create confusion higher up
Note that such names are already used in Linux
with IP blocks from AMBA; Designware blocks, as
I noted, aren't dissimilar (dw_foo.c in at least
That's a much better name. I'ts got technical
content, even! (vs "simple" being "marketing",
including easy confusion with other entities).
All I'll say is that it might
be *too* generic a name. I know I can come up
with current examples of GPIO done via MMIO
(tables) that this driver won't fit at all.
That can probably be worked around via docs and
There'd need to be good docs on what this
gpio-mmio-table interface expects. Some of that
belongs in Kconfig, not much; mostly I'd think
it belongs in driver header comments, but also
some in the patch comment itself. I hear you
strongly implying that there's no generic hardware
doc to reference. (As theree would be if this
block came from the AMBA or DesignWare families.)
Half the thing here is that it's barely IP - it's the sort of thing
that's so trivial to implement that it'd take more time to locate a
suitable IP than to just hook up the output pins to the register map
Essentially all this sort of GPIO controller is is a straight wire
through of a set of register bits to an output signal (especially if you
don't have a separate clear register). It's the first thing a hardware
engineer would think of for implementing this - it's not even copy and
paste really, my understanding is that normally it's just basic plumbing
to wire the relevant signals together.
Verilog ? Its far far more primitive than that. You'll find exactly that
arrangement in prehistoric 8bit micro support chips - eg the 6522. In
fact the only reason I can see for not using it on primitive 8bit micro
No they are implementing trivial common sense logic. It's a bit like
complaining we have multiple drivers that use addition.
I think you need a reality check. Its a VLSI undergraduate project level
device, or was back when they taught undergraduates a sampling of chip
design by drawing the transistors. This is "my first logic design" stuff.