On Thu, Aug 26, 2010 at 10:34:58AM -0700, David Brownell wrote:
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> --- On Thu, 8/26/10, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:

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> > > Just rename it to match the IP block used.

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> > There are zillions of IP blocks that have that interface,

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> If there are "zillions" that suggests the HW
> engineers have version/naming issues just like
> certain software engineers.  Only goes to show
> how close Verilog and VHDL are to software! :)

Half the thing here is that it's barely IP - it's the sort of thing
that's so trivial to implement that it'd take more time to locate a
suitable IP than to just hook up the output pins to the register map
directly.

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> > how exactly do
> > you propose to rename it.

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> My suggestion was to use the name provided/used
> by the hardware engineers.  (E.g. whatever the
> Verilog or VHDL equivalent of a module name is.)

That's not going to happen, nobody's sharing any IP for this.

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> If I understand you correctly, those engineers
> are not reusing a named module; they are at best
> just copying/pasting some Verilog/VHDL and adding
> ASIC/SoC/.../FPGA-specific hacks.  (Which calls into
> question just how much assurance there can be that
> one driver will work reliably for all instances...

Essentially all this sort of GPIO controller is is a straight wire
through of a set of register bits to an output signal (especially if you
don't have a separate clear register).  It's the first thing a hardware
engineer would think of for implementing this - it's not even copy and
paste really, my understanding is that normally it's just basic plumbing
to wire the relevant signals together.
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