On Thu, Aug 26, 2010 at 01:18:29PM +0400, Cyrill Gorcunov wrote:
quoted text > On Thu, Aug 26, 2010 at 1:00 PM, Robert Richter <robert.richter@amd.com> wrote:
> ...
> >
> > This could also be a race in the counter handling code, or we do not
> > proper count the number of handled counters. Maybe 2 counters actually
> > fired but we only noticed one counter and then accidentially cleared
> > the 2nd without processing it.
> >
> > -Robert
> >
>
> Any chance to get it tested on P4 machine since it has a bit
> different design?
Well P4 uses a different pmu irq handler, so I am not sure it will give us
much insight. I haven't noticed this on an AMD or an intel i5 either.
Cheers,
Don
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Messages in current thread:
Re: [PATCH -v3] perf, x86: try to handle unknown nmis with ... , Don Zickus , (Thu Aug 26, 7:31 am)