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These patches add support to the Qualcomm msm8660 target. It currently provides uniprocessor support only, though SMP support is forthcoming. Note that this code is based on top of Gregory Bean's gpiomux code, and won't build until the mach-types are updated. Abhijeet Dharmapurikar (3): GIC: Dont disable INT in ack callback msm: irqs-8x60: interrupt map msm: 8x60: setup correct handlers for private interrupts Daniel Walker (3): arm: mm: add proc info for ScorpionMP msm: add hotplug stub functions msm: allow uart to be conditionally disabled Gregory Bean (1): msm: add MSM8x60 FFA support Jeff Ohlstein (5): msm: timer: support 8x60 timers msm: clock: add dummy clock driver dma: add stub functions for dma features not yet present on 8x60 msm: add build support for msm8x60 target msm: physical offset for MSM8X60 Stepan Moskovchenko (3): msm: Add MSM IOMMU support msm: Platform initialization for the IOMMU driver msm: Platform data for msm8x60 IOMMUs Steve Muckle (9): msm: create config option for proc-comm arm: Kconfig option for ARCH_MSM_SCORPIONMP msm: io: MSM8X60 io support msm: initial irq definitions for MSM8X60 msm: MSM8X60 RUMI3 board support msm: irq: rename existing entry-macro to entry-macro-vic msm: 8x60: gic initialization fixup for RUMI msm: add msm8x60_surf machine msm: MSM8X60 simulator board support arch/arm/Kconfig | 3 +- arch/arm/common/gic.c | 14 - arch/arm/mach-msm/Kconfig | 52 +- arch/arm/mach-msm/Makefile | 20 +- arch/arm/mach-msm/board-msm8x60.c | 102 ++ arch/arm/mach-msm/clock-dummy.c | 54 + arch/arm/mach-msm/devices-msm8x60-iommu.c | 883 ++++++++++ arch/arm/mach-msm/hotplug.c | 22 + arch/arm/mach-msm/include/mach/debug-macro.S | 2 +- arch/arm/mach-msm/include/mach/dma.h | ...
From: Daniel Walker <dwalker@codeaurora.org>
ScorpionMP does not have the SMP/nAMP and TLB ops broadcasting bits in
ACTLR.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
---
arch/arm/mm/proc-v7.S | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..98fd7e5 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -196,6 +196,7 @@ __v7_setup:
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
#endif
+__v7_msm_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
bl v7_flush_dcache_all
@@ -326,6 +327,29 @@ cpu_elf_name:
.section ".proc.info.init", #alloc, #execinstr
+ .type __v7_msm_proc_info, #object
+__v7_msm_proc_info:
+ .long 0x510f0000 @ Required ID value
+ .long 0xff0f0000 @ Mask for ID
+ .long PMD_TYPE_SECT | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ | \
+ PMD_FLAGS
+ .long PMD_TYPE_SECT | \
+ PMD_SECT_XN | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
+ b __v7_msm_setup
+ .long cpu_arch_name
+ .long cpu_elf_name
+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+ .long cpu_v7_name
+ .long v7_processor_functions
+ .long v7wbi_tlb_fns
+ .long v6_user_fns
+ .long v7_cache_fns
+ .size __v7_msm_proc_info, . - __v7_msm_proc_info
+
/*
* Match any ARMv7 processor core.
*/
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
It may be better to move the generic __v7_setup here and have a specific entry for ARM Ltd cores (mask 0xff0f0000 and value 0x410f0000). In general, I would have liked a different way (still ID-based) of handling such issues without duplicating the whole structure. But I see this becoming the standard as proc-v6.S follows it as well. -- Catalin --
I'm not sure I follow you.. Are you saying there are other cpu's that This whole thing was something Russell specifically asked for (and practically wrote for me). Daniel -- Sent by an consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
The SMP/nAMP bit is something specific to the ARM11MPCore and Cortex-A9 processors produced by ARM. If you core doesn't need this, it should use a default __v7_setup without any additional bits being set. I'm not aware of other MP ARM processors produced by other companies Yes, I know and I'm not saying that you should change it in this patch. It's just that I would have liked to only duplicate the setup function rather than the whole procinfo structure. -- Catalin --
So your saying it makes more sense to change the msm entry into the default entry, and make the current default into the ARM11MPCore/Cortex-A9 entry? There's 4 or 5 other cpu's that have SMP but none have had to jump over those bits AFAIK .. Daniel -- Sent by an consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
So my opinion is to not add any specific msm code but make the __v7_setup skip the ACTLR bit setting. Then add an entry for Cortex-A9 Maybe they don't do anything with those bits and writing to them is harmless. They'll complain if their code stops working but it is usually unlikely that people implementing their own v7MP would use the same bits in ACTLR as Cortex-A9. I'm not sure whether someone licensing and manufacturing a Cortex-A9 would use the same manufacturer id (TI folks would know better). If not we could check against 0x000fc090. -- Catalin --
how about this? Naming is of course flexible ..
ScorpionMP does not have the SMP/nAMP and TLB ops broadcasting bits in
ACTLR. These bits are only used on ARM11MPCore and Cortex-A9 from arm.
This patch just makes it so no other arm core ends up getting these
bits set.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
---
arch/arm/mm/proc-v7.S | 26 +++++++++++++++++++++++++-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..e1b5492 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -189,13 +189,14 @@ cpu_v7_name:
* It is assumed that:
* - cache type register is implemented
*/
-__v7_setup:
+__v7_armmp_setup:
#ifdef CONFIG_SMP
mrc p15, 0, r0, c1, c0, 1
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
#endif
+__v7_setup:
adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr}
bl v7_flush_dcache_all
@@ -326,6 +327,29 @@ cpu_elf_name:
.section ".proc.info.init", #alloc, #execinstr
+ .type __v7_armmp_proc_info, #object
+__v7_armmp_proc_info:
+ .long 0x410f0000 @ Required ID value
+ .long 0xff0f0000 @ Mask for ID
+ .long PMD_TYPE_SECT | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ | \
+ PMD_FLAGS
+ .long PMD_TYPE_SECT | \
+ PMD_SECT_XN | \
+ PMD_SECT_AP_WRITE | \
+ PMD_SECT_AP_READ
+ b __v7_armmp_setup
+ .long cpu_arch_name
+ .long cpu_elf_name
+ .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+ .long cpu_v7_name
+ .long v7_processor_functions
+ .long v7wbi_tlb_fns
+ .long v6_user_fns
+ .long v7_cache_fns
+ .size __v7_armmp_proc_info, . - __v7_armmp_proc_info
+
/*
* Match any ARMv7 processor core.
*/
--
1.7.0.4
--
Sent by an consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code ...I cc'ed Santosh as well. I'm not sure whether TI are using a Cortex-A9 Maybe __v7_ca9mp_setup. Future MP processors from ARM may not need this We could restrict it to: .long 0x410fc090 .long 0xff0ffff0 Otherwise the patch looks fine. Thanks. -- Catalin --
Ok, I'll add this. Daniel -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
Yep. OMAP4 CA-9 field is 0x41. Regards, Santosh --
What CPUs (CPU not SoC) are you referring to? CPUs is the core that runs the code. SoC is the CPU with the peripherals. OMAP is not a CPU. OMAP is a SoC. --
I guess I'm referring to the SoC then (in this case all SMP SoC's) .. Daniel --
If you think about it, the only way to do that is to make things even more complicated than they already are by separating out the rest of the structure from the ID, mask, and setup functions. At that point, what if someone has just one change to the other values in the structure? They'll have the same complaint as you have, and they'll want it split in an entirely different way. --
From: Steve Muckle <smuckle@codeaurora.org> ScorpionMP is a configuration of Scorpion processors. It supports local timers. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> --- arch/arm/Kconfig | 3 ++- arch/arm/mach-msm/Kconfig | 2 ++ 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8036e46..d4d9f55 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1173,7 +1173,8 @@ config HOTPLUG_CPU config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ - REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500) + REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500 || \ + ARCH_MSM_SCORPIONMP) default y select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500) help diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 08ed76c..3b9bece 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -39,6 +39,8 @@ config ARCH_MSM_ARM11 bool config ARCH_MSM_SCORPION bool +config ARCH_MSM_SCORPIONMP + bool config MSM_VIC bool -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Steve Muckle <smuckle@codeaurora.org> MSM8X60 has different IO mappings than previous MSMs. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/include/mach/io.h | 1 + arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 21 +++++++++++++++++++++ arch/arm/mach-msm/io.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h index c35b29f..7386e73 100644 --- a/arch/arm/mach-msm/include/mach/io.h +++ b/arch/arm/mach-msm/include/mach/io.h @@ -28,6 +28,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m void msm_map_qsd8x50_io(void); void msm_map_msm7x30_io(void); +void msm_map_msm8x60_io(void); extern unsigned int msm_shared_ram_phys; diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 17209f7..ee58da5 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -35,8 +35,29 @@ * */ + +#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) +#define MSM_QGIC_DIST_PHYS 0x02080000 +#define MSM_QGIC_DIST_SIZE SZ_4K + +#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) +#define MSM_QGIC_CPU_PHYS 0x02081000 +#define MSM_QGIC_CPU_SIZE SZ_4K + +#define MSM_ACC_BASE IOMEM(0xF0002000) +#define MSM_ACC_PHYS 0x02001000 +#define MSM_ACC_SIZE SZ_4K + +#define MSM_GCC_BASE IOMEM(0xF0003000) +#define MSM_GCC_PHYS 0x02082000 +#define MSM_GCC_SIZE SZ_4K + #define MSM_TLMM_BASE IOMEM(0xF0004000) #define MSM_TLMM_PHYS 0x00800000 #define MSM_TLMM_SIZE SZ_16K +#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) +#define MSM_SHARED_RAM_SIZE SZ_1M + + #endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index 1c05060..d36b610 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -100,6 +100,21 @@ void __init ...
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> --- arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 10 +- arch/arm/mach-msm/timer.c | 226 +++++++++++++++++------ 2 files changed, 177 insertions(+), 59 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index ee58da5..1f15bbb 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -35,7 +35,6 @@ * */ - #define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) #define MSM_QGIC_DIST_PHYS 0x02080000 #define MSM_QGIC_DIST_SIZE SZ_4K @@ -56,7 +55,14 @@ #define MSM_TLMM_PHYS 0x00800000 #define MSM_TLMM_SIZE SZ_16K -#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) +#define MSM_TMR_BASE IOMEM(0xF0100000) +#define MSM_TMR_PHYS 0x02000000 +#define MSM_TMR_SIZE (SZ_1M) + +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4) +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) + +#define MSM_SHARED_RAM_BASE IOMEM(0xF0200000) #define MSM_SHARED_RAM_SIZE SZ_1M diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index dec5ca6..e76d869 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -1,6 +1,6 @@ -/* linux/arch/arm/mach-msm/timer.c - * +/* * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -21,6 +21,7 @@ #include <linux/clockchips.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/percpu.h> #include <asm/mach/time.h> #include <mach/msm_iomap.h> @@ -28,7 +29,20 @@ #ifndef MSM_DGT_BASE #define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) #endif + +#ifdef CONFIG_MSM7X00A_USE_GP_TIMER + #define DG_TIMER_RATING 100 + #define MSM_GLOBAL_TIMER MSM_CLOCK_GPT +#else + #define DG_TIMER_RATING 300 + #define ...
From: Steve Muckle <smuckle@codeaurora.org>
On RUMI platform STIs are not enabled by default, contrary to the
GIC spec. The bits for STIs in the enable/enable clear registers
are also RW instead of RO. STIs need to be enabled at initialization
time.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
---
arch/arm/mach-msm/board-msm8x60.c | 21 +++++++++++++++++++++
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 3ab4bd9..c6bf8e3 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -18,6 +18,8 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/io.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -42,9 +44,28 @@ static void __init msm8x60_map_io(void)
static void __init msm8x60_init_irq(void)
{
+ unsigned int i;
+
gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+
+ /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
+ writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
+
+ /* RUMI does not adhere to GIC spec by enabling STIs by default.
+ * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
+ */
+ writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
+
+ /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
+ * as they are configured as level, which does not play nice with
+ * handle_percpu_irq.
+ */
+ for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
+ if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
+ set_irq_handler(i, handle_percpu_irq);
+ }
}
static void __init msm8x60_init(void)
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
Need to add this until real clock support for 8x60 goes in, or else some
drivers won't compile.
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
---
arch/arm/mach-msm/Makefile | 1 +
arch/arm/mach-msm/clock-dummy.c | 54 +++++++++++++++++++++++++++++++++++++++
2 files changed, 55 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-msm/clock-dummy.c
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 64a95ae..ff19e01 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -7,6 +7,7 @@ else
obj-y += irq.o
endif
+obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_MSM_PROC_COMM) += clock.o gpio.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
new file mode 100644
index 0000000..1250d22
--- /dev/null
+++ b/arch/arm/mach-msm/clock-dummy.c
@@ -0,0 +1,54 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/module.h>
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+ return ...From: Steve Muckle <smuckle@codeaurora.org> The existing MSM irq entry macro is specific to a VIC implementation. Renaming this makes room for irq support based on other interrupt controllers. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/include/mach/entry-macro-qgic.S | 96 +++++++++++++++++++++ arch/arm/mach-msm/include/mach/entry-macro-vic.S | 37 ++++++++ arch/arm/mach-msm/include/mach/entry-macro.S | 43 +++------ arch/arm/mach-msm/include/mach/smp.h | 39 +++++++++ 4 files changed, 186 insertions(+), 29 deletions(-) create mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S create mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S create mode 100644 arch/arm/mach-msm/include/mach/smp.h diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S new file mode 100644 index 0000000..092e48e --- /dev/null +++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S @@ -0,0 +1,96 @@ +/* + * Low-level IRQ helper macros + * + * Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/hardware.h> +#include <asm/hardware/gic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =gic_cpu_base_addr + ldr \base, [\base] + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + /* + * The interrupt numbering scheme is defined in the + * interrupt controller spec. To wit: + * + * Migrated the code from ARM MP port to be more consistant + * with interrupt processing , the following still holds true + * however, all interrupts are treated the same regardless of + * if they are local IPI or PPI + * + * Interrupts 0-15 are IPI + * 16-31 are PPI + * (16-18 are the ...
What is CONFIG_REQUEST_IPI, and is it ever defined? --
From: Daniel Walker <dwalker@codeaurora.org>
We don't actually do anything for hotplug yet. This just lets
everything compile, even when hotplug is enabled.
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
---
arch/arm/mach-msm/Makefile | 1 +
arch/arm/mach-msm/hotplug.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-msm/hotplug.c
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index ff19e01..8a01f8a 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -21,4 +21,5 @@ obj-y += gpiomux.o
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-7x00.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-7x00.o
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
new file mode 100644
index 0000000..ba0803a
--- /dev/null
+++ b/arch/arm/mach-msm/hotplug.c
@@ -0,0 +1,22 @@
+/*
+ * Do nothing for now.
+ */
+
+int platform_cpu_kill(unsigned int cpu)
+{
+ return 0;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+ return 0;
+}
+
+void local_timer_stop(void)
+{
+}
+
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
And the point of that is? If you're not supporting hotplug CPU yet, then don't allow it to be enabled. --
How do we do that? I didn't see a easy way to prevent it. Daniel -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
config HOTPLUG_CPU
bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
depends on SMP && HOTPLUG && EXPERIMENTAL
+ depends on !ARCH_MSM
--
So every other SMP does this? I didn't see any other's besides RealView implementing these. I just assumed they all had compile failures. Daniel -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
If no others use it .. We can do this to fix them all. What do you think? diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d4d9f55..6d8cf39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1163,9 +1163,12 @@ config NR_CPUS depends on SMP default "4" +config HAS_HOTPLUG_CPU + bool + config HOTPLUG_CPU bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" - depends on SMP && HOTPLUG && EXPERIMENTAL + depends on SMP && HOTPLUG && EXPERIMENTAL && HAS_HOTPLUG_CPU help Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu. diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index b4575ae..8b5c339 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -11,6 +11,7 @@ config REALVIEW_EB_A9MP bool "Support Multicore Cortex-A9" depends on MACH_REALVIEW_EB select CPU_V7 + select HAS_HOTPLUG_CPU help Enable support for the Cortex-A9MPCore tile on the Realview platform. @@ -19,6 +20,7 @@ config REALVIEW_EB_ARM11MP depends on MACH_REALVIEW_EB select CPU_V6 select ARCH_HAS_BARRIERS if SMP + select HAS_HOTPLUG_CPU help Enable support for the ARM11MPCore tile on the Realview platform. @@ -37,6 +39,7 @@ config MACH_REALVIEW_PB11MP select ARM_GIC select HAVE_PATA_PLATFORM select ARCH_HAS_BARRIERS if SMP + select HAS_HOTPLUG_CPU help Include support for the ARM(R) RealView MPCore Platform Baseboard. PB11MPCore is a platform with an on-board ARM11MPCore and has @@ -74,6 +77,7 @@ config MACH_REALVIEW_PBX select HAVE_PATA_PLATFORM select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM + select HAS_HOTPLUG_CPU help Include support for the ARM(R) RealView PBX platform. -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
If no one else implements it, then you can't suspend, nor can you support kexec. (We should update Kconfig to add this as a dependency.) So if you want these features, you'll need to implement hotplug CPU support. --
I must be wrong then, but I don't see those function anyplace but in Ok .. Daniel -- Sent by an consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Daniel Walker <dwalker@codeaurora.org> Some MSM targets don't select the debug UART in this way. For those we need to disable this selection mechanism. Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 8 +++++++- arch/arm/mach-msm/include/mach/debug-macro.S | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 60ad211..27fc183 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -11,6 +11,7 @@ config ARCH_MSM7X00A select MSM_SMD_PKG3 select CPU_V6 select MSM_PROC_COMM + select HAS_MSM_DEBUG_UART_PHYS config ARCH_MSM7X30 bool "MSM7x30" @@ -20,6 +21,7 @@ config ARCH_MSM7X30 select CPU_V7 select MSM_REMOTE_SPINLOCK_DEKKERS select MSM_PROC_COMM + select HAS_MSM_DEBUG_UART_PHYS config ARCH_QSD8X50 bool "QSD8X50" @@ -29,6 +31,7 @@ config ARCH_QSD8X50 select CPU_V7 select MSM_REMOTE_SPINLOCK_LDREX select MSM_PROC_COMM + select HAS_MSM_DEBUG_UART_PHYS endchoice @@ -41,7 +44,8 @@ config ARCH_MSM_SCORPION bool config ARCH_MSM_SCORPIONMP bool - +config HAS_MSM_DEBUG_UART_PHYS + bool config MSM_VIC bool @@ -95,6 +99,7 @@ config MSM_DEBUG_UART default 2 if MSM_DEBUG_UART2 default 3 if MSM_DEBUG_UART3 +if HAS_MSM_DEBUG_UART_PHYS choice prompt "Debug UART" @@ -112,6 +117,7 @@ choice config MSM_DEBUG_UART3 bool "UART3" endchoice +endif config MSM_SMD_PKG3 bool diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S index 528750f..238c4f1 100644 --- a/arch/arm/mach-msm/include/mach/debug-macro.S +++ b/arch/arm/mach-msm/include/mach/debug-macro.S @@ -19,7 +19,7 @@ #include <mach/hardware.h> #include <mach/msm_iomap.h> -#ifdef CONFIG_MSM_DEBUG_UART +#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS .macro addruart, rx, tmp ...
From: Steve Muckle <smuckle@codeaurora.org> Some builds may not support the proc-comm interface with the baseband processor. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 +++++++ arch/arm/mach-msm/Makefile | 6 ++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 4e79580..08ed76c 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -10,6 +10,7 @@ config ARCH_MSM7X00A select MSM_SMD select MSM_SMD_PKG3 select CPU_V6 + select MSM_PROC_COMM config ARCH_MSM7X30 bool "MSM7x30" @@ -18,6 +19,7 @@ config ARCH_MSM7X30 select MSM_VIC select CPU_V7 select MSM_REMOTE_SPINLOCK_DEKKERS + select MSM_PROC_COMM config ARCH_QSD8X50 bool "QSD8X50" @@ -26,6 +28,8 @@ config ARCH_QSD8X50 select MSM_VIC select CPU_V7 select MSM_REMOTE_SPINLOCK_LDREX + select MSM_PROC_COMM + endchoice config MSM_SOC_REV_A @@ -103,6 +107,9 @@ endchoice config MSM_SMD_PKG3 bool +config MSM_PROC_COMM + bool + config MSM_SMD bool diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index faeb1f9..78fb536 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,8 +1,5 @@ -obj-y += proc_comm.o obj-y += io.o idle.o timer.o dma.o -obj-y += vreg.o obj-y += acpuclock-arm11.o -obj-y += clock.o clock-pcom.o ifdef CONFIG_MSM_VIC obj-y += irq-vic.o @@ -10,10 +7,11 @@ else obj-y += irq.o endif +obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o +obj-$(CONFIG_MSM_PROC_COMM) += clock.o gpio.o obj-$(CONFIG_ARCH_QSD8X50) += sirc.o obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o obj-$(CONFIG_MSM_SMD) += last_radio_log.o - obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o -- ...
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
---
arch/arm/mach-msm/include/mach/dma.h | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 00f9bbf..05583f5 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -32,10 +32,18 @@ struct msm_dmov_cmd {
void *data;
};
+#ifndef CONFIG_ARCH_MSM8X60
void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
-
+#else
+static inline
+void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
+static inline
+void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
+static inline
+int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
+#endif
#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
From: Steve Muckle <smuckle@codeaurora.org> Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 +++++++ arch/arm/mach-msm/Makefile | 1 + arch/arm/mach-msm/board-msm8x60.c | 7 +++++++ 3 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dfa67d8..3017e12 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -98,6 +98,13 @@ config MACH_MSM8X60_RUMI3 help Support for the Qualcomm MSM8x60 RUMI3 emulator. +config MACH_MSM8X60_SURF + depends on ARCH_MSM8X60 + default n + bool "MSM8x60 SURF" + help + Support for the Qualcomm MSM8x60 SURF eval board. + endmenu config MSM_DEBUG_UART diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 17c03fa..1d62025 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-7x00.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o +obj-$(CONFIG_MACH_MSM8X60_SURF) += board-msm8x60.o diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index e2e5a5c..fd953c2 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -78,3 +78,10 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") .init_machine = msm8x60_init, .timer = &msm_timer, MACHINE_END + +MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") + .map_io = msm8x60_map_io, + .init_irq = msm8x60_init_irq, + .init_machine = msm8x60_init, + .timer = &msm_timer, +MACHINE_END -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
The MSM8x60 has a different physical memory offset than other targets. Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> --- arch/arm/mach-msm/include/mach/memory.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index 50c7847..070e17d 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h @@ -23,6 +23,8 @@ #define PHYS_OFFSET UL(0x20000000) #elif defined(CONFIG_ARCH_MSM7X30) #define PHYS_OFFSET UL(0x00200000) +#elif defined(CONFIG_ARCH_MSM8X60) +#define PHYS_OFFSET UL(0x40200000) #else #define PHYS_OFFSET UL(0x10000000) #endif -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Private Peripheral interrupts could be edge triggered or level triggered
depending on the platform. Initialize handlers for these in board file.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
---
arch/arm/mach-msm/board-msm8x60.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index c6bf8e3..e2e5a5c 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -46,7 +46,7 @@ static void __init msm8x60_init_irq(void)
{
unsigned int i;
- gic_dist_init(0, MSM_QGIC_DIST_BASE, 1);
+ gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 +++++++ arch/arm/mach-msm/Makefile | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 27fc183..dfa67d8 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -33,6 +33,13 @@ config ARCH_QSD8X50 select MSM_PROC_COMM select HAS_MSM_DEBUG_UART_PHYS +config ARCH_MSM8X60 + bool "MSM8X60" + select ARCH_MSM_SCORPIONMP + select ARM_GIC + select CPU_V7 + select MSM_V2_TLMM + endchoice config MSM_SOC_REV_A diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 8a01f8a..17c03fa 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -1,11 +1,16 @@ -obj-y += io.o idle.o timer.o dma.o +obj-y += io.o idle.o timer.o +ifndef CONFIG_ARCH_MSM8X60 obj-y += acpuclock-arm11.o +obj-y += gpio.o dma.o +endif ifdef CONFIG_MSM_VIC obj-y += irq-vic.o else +ifndef CONFIG_ARCH_MSM8X60 obj-y += irq.o endif +endif obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Gregory Bean <gbean@codeaurora.org> The MSM8X60 FFA contains different components than the MSM8X60 SURF, and therefore requires a different ARCH type and machine ID. Signed-off-by: Gregory Bean <gbean@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 +++++++ arch/arm/mach-msm/Makefile | 1 + arch/arm/mach-msm/board-msm8x60.c | 7 +++++++ 3 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index d2610a3..d6b83de 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -112,6 +112,13 @@ config MACH_MSM8X60_SIM help Support for the Qualcomm MSM8x60 simulator. +config MACH_MSM8X60_FFA + depends on ARCH_MSM8X60 + default n + bool "MSM8x60 FFA" + help + Support for the Qualcomm MSM8x60 FFA eval board. + endmenu config MSM_DEBUG_UART diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 9fb73ab..c984f4d 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o obj-$(CONFIG_MACH_MSM8X60_SURF) += board-msm8x60.o obj-$(CONFIG_MACH_MSM8X60_SIM) += board-msm8x60.o +obj-$(CONFIG_MACH_MSM8X60_FFA) += board-msm8x60.o diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 7a2ed7f..02d22ea 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -93,3 +93,10 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") .init_machine = msm8x60_init, .timer = &msm_timer, MACHINE_END + +MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") + .map_io = msm8x60_map_io, + .init_irq = msm8x60_init_irq, + .init_machine = msm8x60_init, + .timer = &msm_timer, +MACHINE_END -- 1.7.2.1 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Steve Muckle <smuckle@codeaurora.org> Board configuration for MSM8X60 simulation. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 +++++++ arch/arm/mach-msm/Makefile | 1 + arch/arm/mach-msm/board-msm8x60.c | 10 +++++++++- 3 files changed, 17 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 3017e12..d2610a3 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -105,6 +105,13 @@ config MACH_MSM8X60_SURF help Support for the Qualcomm MSM8x60 SURF eval board. +config MACH_MSM8X60_SIM + depends on ARCH_MSM8X60 + default n + bool "MSM8x60 Simulator" + help + Support for the Qualcomm MSM8x60 simulator. + endmenu config MSM_DEBUG_UART diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 1d62025..9fb73ab 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o obj-$(CONFIG_MACH_MSM8X60_SURF) += board-msm8x60.o +obj-$(CONFIG_MACH_MSM8X60_SIM) += board-msm8x60.o diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index fd953c2..7a2ed7f 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -56,7 +56,8 @@ static void __init msm8x60_init_irq(void) /* RUMI does not adhere to GIC spec by enabling STIs by default. * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. */ - writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); + if (!machine_is_msm8x60_sim()) + writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet * as they are configured as level, which does not play nice with @@ -85,3 +86,10 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") ...
All these 'default n' statements can be removed - n is the default anyway. --
Isn't the behavior different, though? If I do a 'make oldconfig' after a kernel upgrade, new options that don't have defaults will stop and prompt me, whereas ones with a listed default will just select the default without asking. I though the desire was to not have it stop and ask unless it really was something that the user needed to make a decision about. David -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
You always get asked about new options which have an option text - but 'default' sets what you get when you just hit 'enter' on them. --
From: Stepan Moskovchenko <stepanm@codeaurora.org> Register a driver for the MSM IOMMU devices and a driver for the translation context devices. Set up the global IOMMU registers and initialize the context banks. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> --- arch/arm/mach-msm/Makefile | 2 +- arch/arm/mach-msm/iommu_dev.c | 364 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 365 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-msm/iommu_dev.c diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index c984f4d..0d16232 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -12,7 +12,7 @@ obj-y += irq.o endif endif -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o +obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o obj-$(CONFIG_MSM_PROC_COMM) += clock.o gpio.o obj-$(CONFIG_ARCH_QSD8X50) += sirc.o diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c new file mode 100644 index 0000000..59ac7e5 --- /dev/null +++ b/arch/arm/mach-msm/iommu_dev.c @@ -0,0 +1,364 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include ...
From: Stepan Moskovchenko <stepanm@codeaurora.org> Add the platform data for the IOMMUs found on the Qualcomm msm8x60 SoC. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> --- arch/arm/mach-msm/Makefile | 2 +- arch/arm/mach-msm/devices-msm8x60-iommu.c | 883 +++++++++++++++++++++++ arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 32 + 3 files changed, 916 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-msm/devices-msm8x60-iommu.c diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 0d16232..bf9eb38 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -12,7 +12,7 @@ obj-y += irq.o endif endif -obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o +obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o obj-$(CONFIG_MSM_PROC_COMM) += clock.o gpio.o obj-$(CONFIG_ARCH_QSD8X50) += sirc.o diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c new file mode 100644 index 0000000..89b9d44 --- /dev/null +++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c @@ -0,0 +1,883 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, ...
From: Stepan Moskovchenko <stepanm@codeaurora.org> Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> --- arch/arm/mach-msm/include/mach/iommu.h | 103 ++ arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | 1871 ++++++++++++++++++++++++ arch/arm/mach-msm/iommu.c | 597 ++++++++ 3 files changed, 2571 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-msm/include/mach/iommu.h create mode 100644 arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h create mode 100644 arch/arm/mach-msm/iommu.c diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h new file mode 100644 index 0000000..218ef57 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -0,0 +1,103 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#ifndef MSM_IOMMU_H +#define MSM_IOMMU_H + +#include <linux/interrupt.h> + +/* Maximum number of Machine IDs that we are allowing to be mapped to the same + * context bank. The number of MIDs mapped to the same CB does not affect + * performance, but there is a practical limit on how many ...
From: Steve Muckle <smuckle@codeaurora.org> Board configuration for MSM8X60 emulation on RUMI3. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/Kconfig | 7 ++++ arch/arm/mach-msm/Makefile | 2 +- arch/arm/mach-msm/board-msm8x60.c | 59 +++++++++++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-msm/board-msm8x60.c diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 3b9bece..60ad211 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -80,6 +80,13 @@ config MACH_QSD8X50A_ST1_5 help Support for the Qualcomm ST1.5. +config MACH_MSM8X60_RUMI3 + depends on ARCH_MSM8X60 + default n + bool "MSM8x60 RUMI3" + help + Support for the Qualcomm MSM8x60 RUMI3 emulator. + endmenu config MSM_DEBUG_UART diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 78fb536..64a95ae 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -16,8 +16,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o - obj-y += gpiomux.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-7x00.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-7x00.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o +obj-$(CONFIG_MACH_MSM8X60_RUMI3) += board-msm8x60.o diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c new file mode 100644 index 0000000..3ab4bd9 --- /dev/null +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -0,0 +1,59 @@ +/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only ...
Please move to a header file. --
I can move the extern to a header, not sure about the gic_cpu_base_addr. Seems like other machine types have it in C code. Even with a prototype in a header I need to define it somewhere. -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. --
From: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Define the interrupt map in irq-8x60.h
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
---
arch/arm/mach-msm/include/mach/irqs-8x60.h | 225 ++++++++++++++++++++++++++++
1 files changed, 225 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index bef47c9..ab4ad27 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -35,6 +35,231 @@
16-31: PPI (private peripheral interrupts)
32+: SPI (shared peripheral interrupts) */
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
+#define INT_GP_TIMER_EXP (GIC_PPI_START + 1)
+#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2)
+#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3)
+#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
+#define AVS_SVICINT (GIC_PPI_START + 5)
+#define AVS_SVICINTSWDONE (GIC_PPI_START + 6)
+#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8)
+#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9)
+#define SC_AVSCPUXDOWN (GIC_PPI_START + 10)
+#define SC_AVSCPUXUP (GIC_PPI_START + 11)
+#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12)
+/* PPI 13 to 15 are unused */
+
+
+#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
+#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2)
+#define NC (GIC_SPI_START + 3)
+#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
+#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
+#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
+#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
+#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
+#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
+#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
+#define ...From: Steve Muckle <smuckle@codeaurora.org> IRQ assignments are different for MSM8X60 than other existing MSMs. Signed-off-by: Steve Muckle <smuckle@codeaurora.org> --- arch/arm/mach-msm/include/mach/irqs-8x60.h | 42 ++++++++++++++++++++++++++++ arch/arm/mach-msm/include/mach/irqs.h | 2 + 2 files changed, 44 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-msm/include/mach/irqs-8x60.h diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h new file mode 100644 index 0000000..bef47c9 --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -0,0 +1,42 @@ +/* Copyright (c) 2010 Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ...
From: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Unless gic_ack_irq is called from __do_IRQ, interrupt should not
be disabled in the ack function.
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
---
arch/arm/common/gic.c | 14 --------------
1 files changed, 0 insertions(+), 14 deletions(-)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 337741f..7d8ca5a 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
/*
* Routines to acknowledge, disable and enable interrupts
- *
- * Linux assumes that when we're done with an interrupt we need to
- * unmask it, in the same way we need to unmask an interrupt when
- * we first enable it.
- *
- * The GIC has a separate notion of "end of interrupt" to re-enable
- * an interrupt after handling, in order to support hardware
- * prioritisation.
- *
- * We can make the GIC behave in the way that Linux expects by making
- * our "acknowledge" routine disable the interrupt, then mark it as
- * complete.
*/
static void gic_ack_irq(unsigned int irq)
{
- u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
- writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}
--
1.7.2.1
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
--
