On Wed, Aug 18, 2010 at 11:21 AM, stephane eranian
<eranian@googlemail.com> wrote:
quoted text
> Lin,
>
> It should not have chosen  intel_x86_arch to begin with.
> That's where the bug is. Let me fix this.
>
>
Fixed in the git tree, just pull again.
Thanks for reporting this issue.

quoted text
> On Wed, Aug 18, 2010 at 9:46 AM, Lin Ming <ming.m.lin@intel.com> wrote:
>> On P4 machine, intel_x86_arch_support.get_event_info(...) faults because
>> intel_x86_arch_support.pe is NULL.
>>
>> intel_x86_arch_support.pe is set at run time, but P4 does not have arch
>> event support, so intel_x86_arch_support.pe is always NULL.
>>
>> #gdb libpfm4/examples/check_events
>>
>> Program received signal SIGSEGV, Segmentation fault.
>> [Switching to Thread 0xb785caf0 (LWP 3950)]
>> 0x0804d74b in pfm_intel_x86_get_event_info (this=0x81c5f80, idx=0, info=0xbff45f14)
>>    at pfmlib_intel_x86.c:667
>> 667             info->desc  = pe[idx].desc;
>> (gdb) bt
>> #0  0x0804d74b in pfm_intel_x86_get_event_info (this=0x81c5f80, idx=0, info=0xbff45f14)
>>    at pfmlib_intel_x86.c:667
>> #1  0x08049cd3 in pfmlib_parse_event (event=0x804fb7b "PERF_COUNT_HW_CPU_CYCLES", d=0xbff45f7c)
>>    at pfmlib_common.c:676
>> #2  0x08049f3f in pfm_get_event_encoding (str=0x804fb7b "PERF_COUNT_HW_CPU_CYCLES", dfl_plm=8,
>>    fstr=0xbff464d4, idx=0xbff464c8, codes=0xbff464d0, count=0xbff464cc) at pfmlib_common.c:877
>> #3  0x08048dc1 in main (argc=<value optimized out>, argv=0xbff46584) at check_events.c:118
>> (gdb) list
>> 662
>> 663             /*
>> 664              * pmu and idx filled out by caller
>> 665              */
>> 666             info->name  = pe[idx].name;
>> 667             info->desc  = pe[idx].desc;
>> 668             info->code  = pe[idx].code;
>> 669             info->equiv = pe[idx].equiv;
>> 670
>> 671             /* unit masks + modifiers */
>> (gdb)
>>
>> Any fix?
>>
>> Lin Ming
>>
>>
>
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