From: Kevin Wells <wellsk40@gmail.com>
This patch contains the RTC driver for the built-in RTC in
the LPC32XX SoC.
Signed-off-by: Kevin Wells <wellsk40@gmail.com>
Signed-off-by: Durgesh Pattamatta <durgesh.pattamatta@nxp.com>
---
drivers/rtc/rtc-lpc32xx.c | 391 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 391 insertions(+), 0 deletions(-)
create mode 100644 drivers/rtc/rtc-lpc32xx.c
diff --git a/drivers/rtc/rtc-lpc32xx.c b/drivers/rtc/rtc-lpc32xx.c
new file mode 100644
index 0000000..7803c68
--- /dev/null
+++ b/drivers/rtc/rtc-lpc32xx.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/rtc.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+/*
+ * Clock and Power control register offsets
+ */
+#define RTC_UCOUNT 0x00
+#define RTC_DCOUNT 0x04
+#define RTC_MATCH0 0x08
+#define RTC_MATCH1 0x0C
+#define RTC_CTRL 0x10
+#define RTC_INTSTAT 0x14
+#define RTC_KEY 0x18
+#define RTC_SRAM 0x80
+
+#define RTC_MATCH0_EN (1 << 0)
+#define RTC_MATCH1_EN (1 << 1)
+#define RTC_ONSW_MATCH0_EN (1 << 2)
+#define RTC_ONSW_MATCH1_EN (1 << 3)
+#define RTC_SW_RESET (1 << 4)
+#define RTC_CNTR_DIS (1 << 6)
+#define RTC_ONSW_FORCE_HIGH (1 << 7)
+
+#define RTC_MATCH0_INT_STS (1 << 0)
+#define RTC_MATCH1_INT_STS (1 << 1)
+#define RTC_ONSW_INT_STS (1 << 2)
+
+#define ...
