On Wed, 14 Jul 2010, Linus Torvalds wrote:

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> No. As mentioned, there is no such counter in real hardware either.

 There is a 1-bit counter or actually a latch.

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> Look at what happens for the not-nested case:
> 
>  - NMI1 triggers. The CPU takes a fault, and runs the NMI handler with
> NMI's disabled

 Correct.

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>  - NMI2 triggers. Nothing happens, the NMI's are disabled.

 The NMI latch records the second NMI.  Note this is edge-sensitive like 
the NMI line itself.

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>  - NMI3 triggers. Again, nothing happens, the NMI's are still disabled

 Correct.

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>  - the NMI handler returns.
> 
>  - What happens now?

 NMI2 latched above causes the NMI handler to be invoked as the next 
instruction after IRET.  The latch is cleared as the interrupt is taken.

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> How many NMI interrupts do you get? ONE. Exactly like my "emulate it
> in software" approach. The hardware doesn't have any counters for
> pending NMI's either. Why should the software emulation have them?

 Two. :)

  Maciej
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