On Wed, Jul 14, 2010 at 11:08 AM, H. Peter Anvin <hpa@zytor.com> wrote:
quoted text
> [Adding H.J. to the Cc: list]
>
> On 07/14/2010 10:57 AM, Jeremy Fitzhardinge wrote:
>>>>
>>> I/O ports, for example.
>>>
>>
>> Yes, it looks like they should have memory barriers if we want them to
>> be ordered with respect to normal writes; afaict "asm volatile" has
>> never had strict ordering wrt memory ops.
>>
>
> Noone has talked about strict ordering between volatiles and
> (non-volatile) memory ops in general.  I have been talking about
> volatile to volatile ordering, and I thought I'd been very clear about that.
>
> H.J., we're having a debate about the actual semantics of "volatile",
> especially "asm volatile" in gcc.  In particular, I believe that
> volatile operations should not be possible to reorder with regards to
> each other, and the kernel depends on that fact.
>
>        -hpa
>
> P.S: gcc 4.4 seems to handle "const volatile" incorrectly, probably by
> applying CSE to those values.
>
>

There are some discussions on:

http://gcc.gnu.org/ml/gcc-patches/2010-06/msg02001.html
http://gcc.gnu.org/ml/gcc-patches/2010-07/msg00001.html

Are they related?


-- 
H.J.
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