On Sat, Jul 10, 2010 at 1:46 PM, Bryan Hundven <bryanhundven@gmail.com> wrote:
quoted text
> I was able to set eth0 and it's TxRx queues to cpu1, but it is my
> understanding that 0xFFFFFFFF should distribute the interrupts across all
> cpus, much like LOC in my output of /proc/interrupts.
>
> I don't have access to the computer this weekend, but I will provide more
> info on Monday.

That may be chipset dependent, I don't think all chipsets have the
ability to distribute the interrupts like that. Round-robin interrupt
distribution for a given handler isn't optimal for performance anyway
since it causes the relevant cache lines for the interrupt handler to
be ping-ponged between the different CPUs.

quoted text
>
> -bryan
>
> On Jul 9, 2010 5:48 PM, "Robert Hancock" <hancockrwd@gmail.com> wrote:
>
> On 07/09/2010 04:59 PM, Bryan Hundven wrote:
>>
>> Mauro, list,
>>
>> (please CC me in replies, I am not...
>
> Tried changing these files to exclude CPU0?
>
> Have you tried running the irqbalance daemon? That's what you likely want to
> be doing anyway..
>
>> =====8<=====8<=====8<=====8<=====8<=====8<=====8<=====8<=====8<=====
>>
>> =====8<=====8<=====8<==...
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