Re: [PATCH] MIPS: KProbes support v0.1

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From: David Daney
Date: Monday, June 7, 2010 - 12:41 pm

I have a few questions and comments below.  Many of them  may be due to 
my lack of understanding about the internals of KProbes.

David Daney.


On 06/07/2010 09:34 AM, Himanshu Chauhan wrote:
[...]

It might be cleaner without the #ifdef.  These are enum value 
definitions, so it doesn't affect code size.


Can you also explain how the die notifier chain interacts with KProbes 
and why it cannot be a seperate notifier chain?

[...]

The BREAK codes are defined in asm/break.h  This should be added there 
instead.

Why do you use codes (0 and 5) that are already kind of reserved for 
user space debuggers?


You have to call a function in arch/mips/mm/c-* to do this, you cannot 
open code with CACHE instructions as you need to handle CPU quirks and 
SMP.  It is possible that flush_icache_range() or flush_cache_sigtramp() 
would work.  Or we might need something new.

I see you use flush_icache_range() below, why have this definition, it 
looks unused?


[...]

Why this ugliness?  Can't you handle it in do_bp() or  do_trap_or_bp()?


[...]

Need to add or otherwise handle:


#ifdef CONFIG_CPU_CAVIUM_OCTEON
	case lwc2_op: /* This is bbit0 on Octeon */
	case ldc2_op: /* This is bbit032 on Octeon */
	case swc2_op: /* This is bbit1 on Octeon */
	case sdc2_op: /* This is bbit132 on Octeon */
#endif


[...]



This should be folded into do_bp().




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Messages in current thread:
[PATCH] Kprobes support for MIPS architecture., Himanshu Chauhan, (Mon Jun 7, 9:33 am)
[PATCH] MIPS: KProbes support v0.1, Himanshu Chauhan, (Mon Jun 7, 9:34 am)
Re: [PATCH] MIPS: KProbes support v0.1, David Daney, (Mon Jun 7, 12:41 pm)
Re: [PATCH] MIPS: KProbes support v0.1, Himanshu Chauhan, (Tue Jun 8, 10:51 am)
Re: [PATCH] MIPS: KProbes support v0.1, David Daney, (Thu Jun 10, 5:12 pm)