On Wed, 2010-05-19 at 07:16 -0700, Darren Hart wrote:
But that's the point, no interrupts on XICS are reported as edge, even
if they are actually edge somewhere deep in the hardware. I don't think
we have any reliable way to determine what is what.
I'm not really sure either, but I think it's a case of a leaky
abstraction on the part of the hypervisor. Edge interrupts behave as
level as long as you handle the irq before EOI, but if you mask they
don't. But Milton's the expert on that.
True. It's not a fix in general though. I'm worried that we're going to
see the exact same bug for MSI(-X) interrupts.
cheers