Home » Mailing list archives » linux-kernel » 2010 » May » 18

[patch 4/4] x86,perf: P4 PMU -- prepare header for user-space inclusion

Previous thread: [patch 3/4] x86,perf: P4 PMU -- add missing bit in CCCR mask by Cyrill Gorcunov on Tuesday, May 18, 2010 - 2:19 pm. (2 messages)

Next thread: schedule() && prev/current (Was: [PATCH 3/3] Make get_current() __attribute__((const))) by Oleg Nesterov on Tuesday, May 18, 2010 - 2:22 pm. (8 messages)
[view original message]
From: Cyrill Gorcunov
Subject: [patch 4/4] x86,perf: P4 PMU -- prepare header for user-space inclusion
Date: Tuesday, May 18, 2010 - 2:19 pm

The header need to be exported to be able to use P4 PMU
in user space applications (for RAW events mostly).

So before make a real export it should sit under linux
sources just to estimate the convenience of its structure.

Note that cache events are not exported at the moment since
they should be redesigned a bit (we need to export and support
the whole metrics set for those who need them for some wild
experiments).

Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
CC: Lin Ming <ming.m.lin@intel.com>
CC: Stephane Eranian <eranian@google.com>
CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
CC: Ingo Molnar <mingo@elte.hu>
CC: Frederic Weisbecker <fweisbec@gmail.com>
---
 arch/x86/include/asm/perf_event_p4.h |   38 ++++++++++++++++++++++++++---------
 1 file changed, 29 insertions(+), 9 deletions(-)

Index: linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
=====================================================================
--- linux-2.6.git.orig/arch/x86/include/asm/perf_event_p4.h
+++ linux-2.6.git/arch/x86/include/asm/perf_event_p4.h
@@ -5,9 +5,6 @@
 #ifndef PERF_EVENT_P4_H
 #define PERF_EVENT_P4_H
 
-#include <linux/cpu.h>
-#include <linux/bitops.h>
-
 /*
  * NetBurst has perfomance MSRs shared between
  * threads if HT is turned on, ie for both logical
@@ -19,7 +16,6 @@
 #define ARCH_P4_RESERVED_ESCR	(2) /* IQ_ESCR(0,1) not always present */
 #define ARCH_P4_MAX_ESCR	(ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
 #define ARCH_P4_MAX_CCCR	(18)
-#define ARCH_P4_MAX_COUNTER	(ARCH_P4_MAX_CCCR / 2)
 
 #define P4_ESCR_EVENT_MASK	0x7e000000U
 #define P4_ESCR_EVENT_SHIFT	25
@@ -71,10 +67,6 @@
 #define P4_CCCR_THRESHOLD(v)		((v) << P4_CCCR_THRESHOLD_SHIFT)
 #define P4_CCCR_ESEL(v)			((v) << P4_CCCR_ESCR_SELECT_SHIFT)
 
-/* Custom bits in reerved CCCR area */
-#define P4_CCCR_CACHE_OPS_MASK		0x0000003fU
-
-
 /* Non HT mask */
 #define P4_CCCR_MASK				\
 	(P4_CCCR_OVF			|	\
@@ -96,6 +88,17 @@
 	class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
 #define ...
[ message continues ]
[view original message]
From: Ingo Molnar
Subject: Re: [patch 4/4] x86,perf: P4 PMU -- prepare header for user-space inclusion
Date: Wednesday, May 19, 2010 - 12:35 am

Would be much better to create a pure, separate header 
file with hardware event format details, without all these 
ugly #ifdefs mixed into a single file.

Thanks,

	Ingo
--


[ message continues ]
[view original message]
From: Cyrill Gorcunov
Subject: Re: [patch 4/4] x86,perf: P4 PMU -- prepare header for user-space inclusion
Date: Wednesday, May 19, 2010 - 12:41 am

seems reasonable, yes! Drop this patch for a while. Thanks!
--


[ message continues ]
Previous thread: [patch 3/4] x86,perf: P4 PMU -- add missing bit in CCCR mask by Cyrill Gorcunov on Tuesday, May 18, 2010 - 2:19 pm. (2 messages)

Next thread: schedule() && prev/current (Was: [PATCH 3/3] Make get_current() __attribute__((const))) by Oleg Nesterov on Tuesday, May 18, 2010 - 2:22 pm. (8 messages)