On Mon, May 10, 2010 at 06:26:35PM +0800, Lin Ming wrote:
quoted text
> On Mon, 2010-05-10 at 18:18 +0800, Peter Zijlstra wrote:
> > On Mon, 2010-05-10 at 18:11 +0800, Lin Ming wrote:
> > > On Mon, 2010-05-10 at 17:40 +0800, Peter Zijlstra wrote:
> > > > On Mon, 2010-05-10 at 17:27 +0800, Lin Ming wrote:
> > > > > Export pmus via sysfs /sys/devices/system/cpu/pmus/0...N
> > > > > The file name is the pmu id, ie, /sys/devices/system/cpu/pmus/N
> > > > > represents pmu id N.
> > > > > So perf tool can use it to initialize perf_event_attr. 
> > > > 
> > > > Why create a whole new directory, why not:
> > > > 
> > > >  /sys/devices/system/cpu/cpuN/pmu_id ?
> > > 
> > > 
> > > Do you mean /sys/devices/system/cpu/cpuN/pmu_id contain all ids?
> > > 
> > > For example, each cpu has 4 pmus and the file pmu_id shows something
> > > like,
> > > 
> > > #cat /sys/devices/system/cpu/cpu0/pmu_id
> > > 0 1 2 3
> > 
> > No, I'm assuming there is only 1 PMU per CPU. Corey is the expert on
> > crazy hardware though, but I think the sanest way is to extend the CPU
> > topology if there's more structure to it.
> 
> But our goal is to support multiple pmus, don't we need to assume there
> are more than 1 PMU per CPU?
> 
The multiple PMU case still suggests 1 per CPU in most (all?) cases. If
you're thinking of PMUs in the northbridge case this would sit under its
own topology given that most CPUs will have a shared view of it. Do you
have some cases with performance counters in per-CPU memory controllers
or something similar?

quoted text
> How about
> /sys/devices/system/cpu/cpuN/pmu_0
> /sys/devices/system/cpu/cpuN/pmu_1
> /sys/devices/system/cpu/cpuN/pmu_2
> /sys/devices/system/cpu/cpuN/pmu_3
> ....?
> 
If you're following driver model naming conventions, then these should
all be pmu.0, pmu.1, etc, etc.
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