This patch exposes the branch trace buffer to users for sampling.
There are measurements where it is very useful to couple the
instruction address with some path information, e.g, basic
block profiling.
On recent Intel processors, the branch stack is implemented using
the LBR registers. LBR was already used to fixup PEBS. This
patch still allows PEBS fixups with LBR and also exposes LBR
to applications.
There is a new PERF_SAMPLE_BRANCH_STACK sample type. It creates
a sample in the buffer which has the following layout:
{ u64 nr;
{ u64 from, to, flags } lbr[nr]; } && PERF_SAMPLE_BRANCH_STACK
};
Refer to include/linux/perf_event.h to figure out the layout ordering
information.
LBR is configured by default to record ALL taken branches. On some
processors, it is possible to filter the type of branches. This will
be supported in a subsequent patch.
On other processors, the sample type is allowed but will generate a
sample where nr=0 as is the case with other sampling types.
Signed-off-by: Stephane Eranian <eranian@google.com>
--
arch/x86/kernel/cpu/perf_event_intel.c | 13 +++++++++++++
arch/x86/kernel/cpu/perf_event_intel_ds.c | 5 +++++
include/linux/perf_event.h | 8 +++++++-
kernel/perf_event.c | 25 +++++++++++++++++++++++++
4 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f168b40..6b8aa7d 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -562,8 +562,13 @@ static void intel_pmu_disable_event(struct perf_event *event)
x86_pmu_disable_event(event);
+ /*
+ * PEBS implies LBR
+ */
if (unlikely(event->attr.precise))
intel_pmu_pebs_disable(event);
+ else if (unlikely(event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK))
+ intel_pmu_lbr_disable(event);
}
static void intel_pmu_enable_fixed(struct ...
