Re: [PATCH 4/5] x86, cacheinfo: Make L3 cache info per node

Previous thread: [PATCH net-next] net/l2tp/l2tp_debugfs.c: Convert NIPQUAD to %pI4 by Joe Perches on Thursday, April 15, 2010 - 9:41 am. (2 messages)

Next thread: [PATCH 0/5] AMD L3 cache index disable fixes for .35 by Borislav Petkov on Thursday, April 15, 2010 - 9:40 am. (6 messages)
From: Borislav Petkov
Date: Thursday, April 15, 2010 - 9:41 am

From: Borislav Petkov <borislav.petkov@amd.com>

Currently, we're allocating L3 cache info and calculating indices for
each online cpu which is clearly superfluous. Instead, we need to do
this per-node as is each L3 cache.

No functional change, only per-cpu memory savings.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c |   49 +++++++++++++++++++++++---------
 1 files changed, 35 insertions(+), 14 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index ff663ca..c42b5c5 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -307,19 +307,20 @@ struct _cache_attr {
 };
 
 #ifdef CONFIG_CPU_SUP_AMD
+
+/* max 8 nodes on a system */
+static struct amd_l3_cache * __cpuinitdata l3_caches[8];
+
+/*
+ * We're called over smp_call_function_single() and
+ * therefore are on the correct cpu.
+ */
 static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
 {
-	/*
-	 * We're called over smp_call_function_single() and therefore
-	 * are on the correct cpu.
-	 */
-	int cpu = smp_processor_id();
-	int node = cpu_to_node(cpu);
-	struct pci_dev *dev = node_to_k8_nb_misc(node);
 	unsigned int sc0, sc1, sc2, sc3;
 	u32 val = 0;
 
-	pci_read_config_dword(dev, 0x1C4, &val);
+	pci_read_config_dword(l3->dev, 0x1C4, &val);
 
 	/* calculate subcache sizes */
 	l3->subcaches[0] = sc0 = !(val & BIT(0));
@@ -328,13 +329,31 @@ static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
 	l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
 
 	l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
+}
+
+static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
+{
+	struct amd_l3_cache *l3;
+	struct pci_dev *dev = node_to_k8_nb_misc(node);
+
+	l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
+	if (!l3) {
+		printk(KERN_WARNING "Error allocating L3 struct\n");
+		return NULL;
+	}
 
 ...
From: H. Peter Anvin
Date: Wednesday, April 21, 2010 - 1:46 pm

This makes me very nervous.  Where does this limit come from?  It
appears completely arbitrary and seems like begging for problems in the
future.

	-hpa
--

From: Borislav Petkov
Date: Wednesday, April 21, 2010 - 2:05 pm

From: "H. Peter Anvin" <hpa@zytor.com>

Right. So, we currently have a 3-bit field for the node id of each node,
in conjunction with the L3 cache this means one L3 cache per node. It is
located in F0x60[2:0]. This field is setup to the proper value by the
BIOS.

But yeah, I see your point. I could try initializing it dynamically
per system so that there are no out of bounds accesses. Let me cook up
something tomorrow.

-- 
Regards/Gruss,
Boris.

--
Advanced Micro Devices, Inc.
Operating Systems Research Center
--

Previous thread: [PATCH net-next] net/l2tp/l2tp_debugfs.c: Convert NIPQUAD to %pI4 by Joe Perches on Thursday, April 15, 2010 - 9:41 am. (2 messages)

Next thread: [PATCH 0/5] AMD L3 cache index disable fixes for .35 by Borislav Petkov on Thursday, April 15, 2010 - 9:40 am. (6 messages)