On 03/22/2010 08:20 AM, Colin King wrote:
quoted text
> "If software clears the PS (page size) bit in a present PDE (page directory
> entry), that will cause linear addresses mapped through this PDE to use
> 4-KByte pages instead of using a large page after old TLB entries are
> invalidated. Due to this erratum, if a code fetch uses this PDE before the
> TLB entry for the large page is invalidated then it may fetch from a different
> physical address than specified by either the old large page translation or
> the new 4-KByte page translation. This erratum may also cause speculative code
> fetches from incorrect addresses."
>    

Does this only affect non-PAE 32-bit?  Or does it also affect 3 and 4 
level pagetables with 2MB large pages?

     J
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