From: Justin Piszcz <jpiszcz@lucidpixels.com>
Date: Tue, Mar 30, 2010 at 04:00:48AM -0400

Hi,

[..]

quoted text
> >>I see the following errors:
> >>
> >>EDAC MC0: CE page 0x8abba, offset 0xa10, grain 8, syndrome 0x4758, row 0, channel 0, label "": k8_edac
> >
> >It looks like it is the first DIMM on your mainboard, i.e., whichever
> >gets mapped to channel 0 of the DCT.
> >
> >Sigh, someday we'll have a better mapping, hopefully, ... :|
> >
> >>EDAC MC0: CE - no information available: k8_edac Error Overflow set
> >>EDAC k8 MC0: extended error code: ECC chipkill x4 error
> >>EDAC k8 MC0: general bus error: participating processor(local node origin), time-out(no timeout) memory transaction type(generic read), mem or i/o(mem access), cache level(generic)
> >>
> >>Is it possible to use the page or offset to calculate which DIMM is having a
> >>problem?

[..]

quoted text
> Thanks, how did you make that calculation?

well, you seem to have a k8 system which means a single DRAM controller
with two channels. Assuming the output "row 0 channel 0" above is
correct (you're using the old k8_edac driver), all sane motherboard
layouts map channel 0 of the DCT to the first logical DIMM and row 0
means chip select row 0 which should be the first rank of the first
DIMM. What DIMMs are you using, by the way (exact part number)?

You can verify this after removing DIMM0 and checking whether you
still get those errors. Also, it would be helpful if you enabled
CONFIG_EDAC_DEBUG and CONFIG_EDAC_DEBUG_VERBOSE (if it existed then) and
send me the whole dmesg of the machine - it should dump the whole memory
configuration.

But as I said before, we need to have better mapping but I'll have to
have some free time first to be able to do it :)

-- 
Regards/Gruss,
Boris.

--
Advanced Micro Devices, Inc.
Operating Systems Research Center
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