The CrystalHD device driver assumes a little endian host. In order to verify future work on
endianess-independence, this patch adds printk's to track the register access to the device.
This helps verify bitfield endianess correctness as well as any hard-coded assumptions in
the driver code.
Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
--- git.orig/drivers/staging/crystalhd/crystalhd_misc.c 2010-03-21 16:05:52.000000000 +0100
+++ git/drivers/staging/crystalhd/crystalhd_misc.c 2010-03-23 13:44:45.324121364 +0100
@@ -140,12 +140,14 @@
*/
uint32_t bc_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off)
{
+ uint32_t val;
if (!adp || (reg_off > adp->pci_mem_len)) {
BCMLOG_ERR("dec_rd_reg_off outof range: 0x%08x\n", reg_off);
return 0;
}
-
- return readl(adp->addr + reg_off);
+ val = readl(adp->addr + reg_off);
+ printk(KERN_DEBUG "bc_dec_reg_rd(): read(0x%p) = 0x%08x\n", adp->addr + reg_off, val);
+ return val;
}
/**
@@ -167,6 +169,7 @@
BCMLOG_ERR("dec_wr_reg_off outof range: 0x%08x\n", reg_off);
return;
}
+ printk(KERN_DEBUG "bc_dec_reg_wr(): writel(0x%08x @ 0x%p).\n", val, adp->addr + reg_off);
writel(val, adp->addr + reg_off);
udelay(8);
}
@@ -186,11 +189,14 @@
*/
uint32_t crystalhd_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off)
{
+ uint32_t val;
if (!adp || (reg_off > adp->pci_i2o_len)) {
- BCMLOG_ERR("link_rd_reg_off outof range: 0x%08x\n", reg_off);
+ printk(KERN_DEBUG "link_rd_reg_off outof range: 0x%08x\n", reg_off);
return 0;
}
- return readl(adp->i2o_addr + reg_off);
+ val = readl(adp->i2o_addr + reg_off);
+ printk(KERN_DEBUG "crystalhd_reg_rd(): read(0x%p) = 0x%08x\n", adp->i2o_addr + reg_off, val);
+ return val;
}
/**
@@ -213,6 +219,7 @@
BCMLOG_ERR("link_wr_reg_off outof range: 0x%08x\n", reg_off);
return;
}
+ printk(KERN_DEBUG "crystalhd_reg_wr(): writel(0x%08x @ 0x%p).\n", val, adp->i2o_addr + reg_off);
writel(val, adp->i2o_addr + reg_off);
}
--
