* Lin Ming <ming.m.lin@intel.com> wrote:

quoted text
> Add cache events in p4 PMU.
> 
> Move the HT bit setting code from p4_pmu_event_map to p4_hw_config.
> So the cache events can get HT bit set correctly.
> 
> Tested on my P4 desktop, below 6 cache events work.
> L1-dcache-load-misses
> LLC-load-misses
> dTLB-load-misses
> dTLB-store-misses
> iTLB-loads
> iTLB-load-misses
> 
> Signed-off-by: Lin Ming <ming.m.lin@intel.com>
> ---
>  arch/x86/include/asm/msr-index.h     |    2 +
>  arch/x86/include/asm/perf_event_p4.h |   10 ++
>  arch/x86/kernel/cpu/perf_event_p4.c  |  153 ++++++++++++++++++++++++++++++++--
>  3 files changed, 159 insertions(+), 6 deletions(-)

i tried it on a Pentium-D box, and it works pretty well:

rhea:/home/mingo/tip> perf stat -a sleep 1

 Performance counter stats for 'sleep 1':

    2003.237268  task-clock-msecs         #      2.000 CPUs 
             11  context-switches         #      0.000 M/sec
              2  CPU-migrations           #      0.000 M/sec
            174  page-faults              #      0.000 M/sec
          47361  cycles                   #      0.024 M/sec  (scaled from 52.83%)
            430  instructions             #      0.009 IPC    (scaled from 74.58%)
          23873  branches                 #      0.012 M/sec  (scaled from 96.70%)
            193  branch-misses            #      0.808 %      (scaled from 49.64%)
            867  cache-references         #      0.000 M/sec  (scaled from 49.69%)
            504  cache-misses             #      0.000 M/sec  (scaled from 49.58%)

    1.001411586  seconds time elapsed

So i've applied your patches. Cyrill, what do you think?

	Ingo
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