On Mon, 01 Mar 2010 14:14:36 +0800
Huang Ying <ying.huang@intel.com> wrote:

quoted text
> To take advantage of the hardware pipeline implementation of AES-NI
> instructions. CTR mode cryption is implemented in ASM to schedule
> multiple AES-NI instructions one after another. This way, some latency
> of AES-NI instruction can be eliminated.
> 
> Performance testing based on dm-crypt should 50% reduction of
> ecryption/decryption time.
> 
> ...
>
> +/*
> + * _aesni_inc_init:	internal ABI
> + *	setup registers used by _aesni_inc
> + * input:
> + *	IV
> + * output:
> + *	CTR:	== IV, in little endian
> + *	TCTR_LOW: == lower qword of CTR
> + *	INC:	== 1, in little endian
> + *	BSWAP_MASK == endian swapping mask
> + */
> +_aesni_inc_init:
> +	movaps .Lbswap_mask, BSWAP_MASK
> +	movaps IV, CTR
> +	PSHUFB_XMM BSWAP_MASK CTR
> +	mov , TCTR_LOW
> +	movq TCTR_LOW, INC
> +	movq CTR, TCTR_LOW

^^ these two lines don't assemble with gas 2.16.1:

arch/x86/crypto/aesni-intel_asm.S: Assembler messages:
arch/x86/crypto/aesni-intel_asm.S:752: Error: suffix or operands invalid for `movq'
arch/x86/crypto/aesni-intel_asm.S:753: Error: suffix or operands invalid for `movq'

quoted text
> +	ret

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