>
>> Does the ia64 dmar_msi_set_affinity() need the same fix?
>
>No.
>
>>
>> Why do we have both x2apic_enabled() and x2apic_mode? They
>> seem sort of redundant. (Not related to this patch, of course.)
>
>BIOS can handover to OS in x2apic mode in some cases. x2apic_enabled()
>is used to check for that and it reads the MSR to check the status. Some
>early portions of the kernel boot will use it.
>
>For all others, we should be using x2apic_mode.
>
>thanks,
>suresh
>---
>
>From: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
>Subject: x86, vtd: fix the vt-d fault handling irq migration in the x2apic
>mode
>
>In x2apic mode, we need to set the upper address register of the fault
>handling interrupt register of the vt-d hardware. Without this
>irq migration of the vt-d fault handling interrupt is broken.
>
>Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
>Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
>Cc:
stable@kernel.org [v2.6.32+]
>---
> arch/x86/kernel/apic/io_apic.c | 1 +
> 1 file changed, 1 insertion(+)
>
>Index: tip/arch/x86/kernel/apic/io_apic.c
>===================================================================
>--- tip.orig/arch/x86/kernel/apic/io_apic.c
>+++ tip/arch/x86/kernel/apic/io_apic.c
>@@ -3367,6 +3367,7 @@ dmar_msi_set_affinity(struct irq_data *d
> msg.data |= MSI_DATA_VECTOR(cfg->vector);
> msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
> msg.address_lo |= MSI_ADDR_DEST_ID(dest);
>+ msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
>
> dmar_msi_write(irq, &msg);
>
