On Fri, 2010-11-19 at 12:03 +0000, Will Deacon wrote:
quoted text
> On Fri, 2010-11-19 at 11:27 +0000, Peter Zijlstra wrote:
> > > So this is the opposite of what we're doing on ARM. Our
> > > approach is to ignore events that are OFF (or in the ERROR
> > > state) or that belong to a different PMU. We do this by
> > > allowing them to *pass* validation (i.e. by returning 1 above).
> > > This means that we won't unconditionally fail a mixed event group.
> > >
> > > x86 does something similar in the collect_events function.
> > 
> > Right, note that the generic code only allows mixing with software
> > events, so simply accepting them is ok as software events give the
> > guarantee they're always schedulable.
> > 
> > 
> 
> Ok. Initially it was software events that I had in mind, but does
> this constraint prevent you from grouping CPU events with events
> for other PMUs within the system? For external L2 cache controllers
> with their own PMUs, it would be desirable to group some L2 events
> with L1 events on a different PMU.
> 
> If each PMU can validate its own events and ignore others then it
> sounds like it should be straightforward...

Getting them all scheduled on the hardware at the same time will be
'interesting'.. therefore we currently don't allow for this. The current
code would pretty much result in such a group being starved if there
were other contenders.
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