On Mon, 15 Nov 2010 11:43:12 -0600
Kumar Gala <galak@kernel.crashing.org> wrote:

quoted text
> 
> On Nov 15, 2010, at 10:13 AM, Timur Tabi wrote:
> 
> > On Mon, Nov 15, 2010 at 9:16 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
> > 
> >> The programming model (if you look at the free-space in the registers and data structures) supports a 64-bit address.  I'm trying to avoid changing the driver in the future if we have >36-bit.  However this is such a minor worry that I'll stop and just ack the patch as is.
> > 
> > I must still be missing something.  I'm looking at the description of
> > the SATR register in the MPC8572 RM, and it shows this:
> > 
> > 0 - 3 |   4 - 5   |     6     |   7  |   8 - 11  |   12 - 15  | 16-21 | 22-31
> > ---  | STFLOWLVL | SPCIORDER | SSME | STRANSINT | SREADTTYPE |  ---  |  ESAD
> > 
> > The most that we can extend ESAD to is 16 bits, for a total of a
> > 48-bit physical address.  Where are the other 16 bits supposed to go?
> 
> I was looking at the link addresses.  I stand corrected so our max is 48-bits.

Looks like 42 bits -- just because bits 16-21 could be used to extend
ESAD doesn't mean that they have been.

-Scott

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