On Fri, 2010-11-12 at 11:49 +0100, Stephane Eranian wrote:
quoted text
> The difficulty with PEBS-LL (load latency) is not so much the encoding of the
> latency. It is more how to expose the data back to user. You get a full PEBS
> record for each miss. So you get the PEBS machine state + data addr, miss
> latency, and data source (where did the line come from). We have already
> discussed how to expose machine state in general. I'll work on a patch for this.

Frederic was working on this PERF_SAMPLE_REGS stuff as well for his copy
the stack top and let dwarfs go wild at it patches.

quoted text
> So we can get the general PEBS machine state out. However, the question is
> how do we expose data addr, latency, data source? We can reuse the
> SAMPLE_ADDR for the data address. Sample IP would point to the load
> instruction (with help from LBR to correct the off by one issue). For
> the latency

Right, PERF_SAMPLE_IP and PERF_SAMPLE_ADDR 

quoted text
> and data source, I proposed using pseudo regs and leveraging the sampled machine
> state mechanism. An alternative may be to define a new record type that would b
> generic enough to be reusable, for instance { instr_addr, data_addr,
> latency, data_src, flags; }. 

I'm not sure I like the idea of pseudo regs.. I'm afraid it'll get messy
quite quickly. Load-latency is a bit like IBS that way, terribly messy.


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