On Wednesday, October 27, 2010 3:52 AM : Marc Kleine-Budde and Wolfgang Grandegge wrote:
The following is some inarticulate points I have for your questions.
Please give me more information.
Uh, I can't understand your intention.
Please show in detail.
This processing does configuration for all message objects.
This loop is for waiting for all tx Message Object completion.
This is Topcliff CAN HW specification.
Uh,le32_to_cpu have been used already here.
I can't understand your intention.
Please show in detail.
When accessing read/write from/to Message RAM,
Since it takes much time for transferring between Register and Message RAM,
SW must check busy flag of CAN register.
This is a Topcliff HW specification.
I can't understand your intention.
pdev(struct pci_dev) doesn't have "name" member.
Please show in detail.
Thanks, Tomoya(OKI SEMICONDUCTOR CO., LTD.)
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