Re: [PATCH 2/2]x86: spread tlb flush vector between nodes

Previous message: [thread] [date] [author]
Next message: [thread] [date] [author]
From: Andi Kleen
Date: Wednesday, October 20, 2010 - 5:18 am

On Wed, Oct 20, 2010 at 02:08:32PM +0200, Peter Zijlstra wrote:

Not sure what your point is? 

I believe non x86 server processors have similar cache
layouts as the one I described, occasionally with another
cache level, and should do well with a similar setup.

For non server it typically doesn't matter too much
because there are not enough cores.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only.
--
Previous message: [thread] [date] [author]
Next message: [thread] [date] [author]

Messages in current thread:
Re: [PATCH 2/2]x86: spread tlb flush vector between nodes, Eric Dumazet, (Tue Oct 19, 10:16 pm)
Re: [PATCH 2/2]x86: spread tlb flush vector between nodes, Peter Zijlstra, (Wed Oct 20, 4:20 am)
Re: [PATCH 2/2]x86: spread tlb flush vector between nodes, Peter Zijlstra, (Wed Oct 20, 5:08 am)
Re: [PATCH 2/2]x86: spread tlb flush vector between nodes, Andi Kleen, (Wed Oct 20, 5:18 am)
[tip:x86/mm] x86: Spread tlb flush vector between nodes, tip-bot for Shaohua Li, (Wed Oct 20, 4:07 pm)