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Re: [PATCH resend 5/9] MIPS: sync after cacheflush

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From: Gleb O. Raiko
Subject: Re: [PATCH resend 5/9] MIPS: sync after cacheflush
Date: Tuesday, October 19, 2010 - 3:15 am

On 19.10.2010 13:17, Ralf Baechle wrote:

I meant another piece:

"For implementations which implement multiple level of caches  ... 
<speaking about inclusive caches here> ... The software must place a 
SYNC instruction after the CACHE instruction whenever there are possible 
writebacks from the inner cache to ensure that the writeback data is 
resident in the outer cache before operating on the
outer cache. ... <the rest of statement is a bogeyman story about not 
doing so>

For implementations which implement muliple level of caches without the 
inclusion property, the use of a SYNC instruction after the CACHE 
instruction is still needed whenever writeback data has to be resident 
in the next level of memory hierarchy."

It seems the last sentence shall be also applied for inclusive caches too.

Gleb.
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[PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm47xx/ ..., Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH 3/9] MIPS: Add BMIPS CP0 register definitions, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH 4/9] MIPS: Install handlers for software IRQs, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 6/9] MIPS: pfn_valid() is broken on low memo ..., Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 8/9] MIPS: Honor L2 bypass bit, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 processors, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
Re: [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm4 ..., Florian Fainelli, (Sun Oct 17, 9:59 am)
Re: [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig, Florian Fainelli, (Sun Oct 17, 10:01 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Mon Oct 18, 6:44 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 11:34 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Mon Oct 18, 12:19 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 12:41 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Mon Oct 18, 3:50 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Mon Oct 18, 5:03 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Mon Oct 18, 5:45 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 5:51 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Mon Oct 18, 5:57 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Tue Oct 19, 1:54 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Tue Oct 19, 2:17 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Tue Oct 19, 3:15 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Tue Oct 19, 5:34 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Tue Oct 19, 6:30 am)
Re: [PATCH resend 8/9] MIPS: Honor L2 bypass bit, Ralf Baechle, (Tue Oct 19, 9:16 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Tue Oct 19, 1:11 pm)
Re: [PATCH 1/9] MIPS: Decouple BMIPS CPU support from bcm4 ..., Ralf Baechle, (Wed Oct 20, 12:19 am)
Re: [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions, Ralf Baechle, (Wed Oct 20, 12:23 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Wed Oct 20, 1:05 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Wed Oct 20, 10:26 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Thu Oct 21, 1:52 am)
Re: [PATCH resend 9/9] MIPS: Allow UserLocal on MIPS_R1 pr ..., Ralf Baechle, (Thu Oct 21, 7:32 am)
Re: [PATCH 4/9] MIPS: Install handlers for software IRQs, Ralf Baechle, (Thu Oct 21, 7:44 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Sat Oct 23, 10:12 pm)