[PATCH resend 6/9] MIPS: pfn_valid() is broken on low memory HIGHMEM systems

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From: Kevin Cernekee
Date: Saturday, October 16, 2010 - 2:22 pm

pfn_valid() compares the PFN to max_mapnr:

        __pfn >= min_low_pfn && __pfn < max_mapnr;

On HIGHMEM kernels, highend_pfn is used to set the value of max_mapnr.
Unfortunately, highend_pfn is left at zero if the system does not
actually have enough RAM to reach into the HIGHMEM range.  This causes
pfn_valid() to always return false, and when debug checks are enabled
the kernel will fail catastrophically:

Memory: 22432k/32768k available (2249k kernel code, 10336k reserved, 653k data, 1352k init, 0k highmem)
NR_IRQS:128
kfree_debugcheck: out of range ptr 81c02900h.
Kernel bug detected[#1]:
Cpu 0
$ 0   : 00000000 10008400 00000034 00000000
$ 4   : 8003e160 802a0000 8003e160 00000000
$ 8   : 00000000 0000003e 00000747 00000747
...

On such a configuration, max_low_pfn should be used to set max_mapnr.

This was seen on 2.6.34.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/mm/init.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 2efcbd2..18183a4 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -370,7 +370,7 @@ void __init mem_init(void)
 #ifdef CONFIG_DISCONTIGMEM
 #error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
 #endif
-	max_mapnr = highend_pfn;
+	max_mapnr = highend_pfn ? : max_low_pfn;
 #else
 	max_mapnr = max_low_pfn;
 #endif
-- 
1.7.0.4

--
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Messages in current thread:
[PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH 3/9] MIPS: Add BMIPS CP0 register definitions, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH 4/9] MIPS: Install handlers for software IRQs, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 6/9] MIPS: pfn_valid() is broken on low memo ..., Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH v2 resend 7/9] MIPS: Move FIXADDR_TOP into spaces.h, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
[PATCH resend 8/9] MIPS: Honor L2 bypass bit, Kevin Cernekee, (Sat Oct 16, 2:22 pm)
Re: [PATCH 2/9] MIPS: Add BMIPS processor types to Kconfig, Florian Fainelli, (Sun Oct 17, 10:01 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Mon Oct 18, 6:44 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 11:34 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Mon Oct 18, 12:19 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 12:41 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Mon Oct 18, 3:50 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Mon Oct 18, 5:03 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Mon Oct 18, 5:45 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Kevin Cernekee, (Mon Oct 18, 5:51 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Mon Oct 18, 5:57 pm)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Tue Oct 19, 1:54 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Tue Oct 19, 2:17 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Tue Oct 19, 3:15 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Ralf Baechle, (Tue Oct 19, 5:34 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Shinya Kuribayashi, (Tue Oct 19, 6:30 am)
Re: [PATCH resend 8/9] MIPS: Honor L2 bypass bit, Ralf Baechle, (Tue Oct 19, 9:16 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Tue Oct 19, 1:11 pm)
Re: [PATCH 3/9] MIPS: Add BMIPS CP0 register definitions, Ralf Baechle, (Wed Oct 20, 12:23 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Wed Oct 20, 1:05 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Wed Oct 20, 10:26 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Gleb O. Raiko, (Thu Oct 21, 1:52 am)
Re: [PATCH resend 5/9] MIPS: sync after cacheflush, Maciej W. Rozycki, (Sat Oct 23, 10:12 pm)