Ok, I just measured this on the 200 MHz S3C24A0, when running the SDIO
bus at 10 MHz, the longest time I saw the driver spend in the pio_read
function was ~10us. I guess that means that the hardware managed to
empty the fifo enough to do yet another spin through the loop. So with
a faster SDIO clock the time spent in pio_read ought to go up, and for a
long transfer it could grow without bounds.
I also tried to run the code with the schedule_tasklet still there, and
then I saw ~13us as the longest time spent in the loop, and every now
and then there was a ~10ms gap when the clock stopped.
If we have working DMA, I think the PIO tasklet is unneccesary, then
we'll do PIO for short transfers which won't affect latency much, and
use DMA for long transfers that would have affected latency if done with
PIO from interrupt context.
/Christer
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