On Mon, Sep 29, 2008 at 03:33:11PM +0200, Joerg Roedel wrote:

quoted text
> > Nobody cares about the performance of dma_alloc_coherent. Only the
> > performance of map_single/map_sg matters.
> >
> > I'm not sure how expensive the hypercalls are, but they are more
> > expensive than bounce buffering coping lots of data for every
> > I/Os?
> 
> I don't think that we can avoid bounce buffering into the guests at
> all (with and without my idea of a paravirtualized IOMMU) when we
> want to handle dma_masks and requests that cross guest physical
> pages properly.

It might be possible to have a per-device slow or fast path, where the
fast path is for devices which have no DMA limitations (high-end
devices generally don't) and the slow path is for devices which do.

quoted text
> With mapping/unmapping through hypercalls we add the world-switch
> overhead to the copy-overhead. We can't avoid this when we have no
> hardware support at all. But already with older IOMMUs like Calgary
> and GART we can at least avoid the world-switch. And since, for
> example, every 64 bit capable AMD processor has a GART we can make
> use of it.

It should be possible to reduce the number and overhead of hypercalls
to the point where their cost is immaterial. I think that's
fundamentally a better approach.

Cheers,
Muli
-- 
The First Workshop on I/O Virtualization (WIOV '08)
Dec 2008, San Diego, CA, http://www.usenix.org/wiov08/
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