Jesse Barnes wrote:I've been experimenting with unmapping flash space until its actually needed, e.g., in the functions that use the E1000_READ_FLASH and E1000_WRITE_FLASH macros. Along the way I looked at how flash write cycles are initiated because I was having a hard time believing that having flash space mapped was part of the root cause. However, it looks like its pretty simple to initiate a write or erase cycle. All of the required action bits in ICH_FLASH_HSFSTS and ICH_FLASH_HSFCTL must be 1, and these 2 register are in the correct order if X was writing 0xff in ascending order. Just a thought. rtg -- Tim Gardner timg@tpi.com www.tpi.com OR 503-601-0234 x102 MT 406-443-5357 --
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