Hmm, I've been pretty spoiled by x86 mostly ording things correctly, and
the not x86 boxes I've used has mostly been UP.
But, with that, with a global atomic counter, and the following trace:
cpu 0: trace_point_a
cpu 1: trace_point_c
cpu 0: trace_point_b
cpu 1: trace_point_d
Could the event a really come after event d, even though we already hit
event b?
But I guess you are stating the fact that what the computer does
internally, no one really knows. Without the help of real memory barriers,
ording of memory accesses is mostly determined by tarot cards.
But basically, the perceived result of assembly commands is suppose to be
accurate at the user level. The traces that I've used not only shows the
order (or perceived order) of events, but also the output of the corrupted
data when the race happens. Usually with the two together, you can pretty
much guarantee that the traced events actually did occur in the order
presented.
But without some perceived accurate ording, even when you do see the
corrupted data, the events can easily be misleading, even on an arch that
usually orders the events as seen by the user.
-- Steve
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