[PATCH 05/23] AMD IOMMU: align alloc_coherent addresses properly

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From: Joerg Roedel
Date: Wednesday, September 17, 2008 - 9:52 am

The API definition for dma_alloc_coherent states that the bus address
has to be aligned to the next power of 2 boundary greater than the
allocation size. This is violated by AMD IOMMU so far and this patch
fixes it.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
---
 arch/x86/kernel/amd_iommu.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 7e9e4e7..fdec963 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -383,7 +383,8 @@ static unsigned long dma_mask_to_pages(unsigned long mask)
  */
 static unsigned long dma_ops_alloc_addresses(struct device *dev,
 					     struct dma_ops_domain *dom,
-					     unsigned int pages)
+					     unsigned int pages,
+					     unsigned long align_mask)
 {
 	unsigned long limit = dma_mask_to_pages(*dev->dma_mask);
 	unsigned long address;
@@ -400,10 +401,10 @@ static unsigned long dma_ops_alloc_addresses(struct device *dev,
 	}
 
 	address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
-			0 , boundary_size, 0);
+				   0 , boundary_size, align_mask);
 	if (address == -1) {
 		address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
-				0, boundary_size, 0);
+				0, boundary_size, align_mask);
 		dom->need_flush = true;
 	}
 
@@ -787,17 +788,22 @@ static dma_addr_t __map_single(struct device *dev,
 			       struct dma_ops_domain *dma_dom,
 			       phys_addr_t paddr,
 			       size_t size,
-			       int dir)
+			       int dir,
+			       bool align)
 {
 	dma_addr_t offset = paddr & ~PAGE_MASK;
 	dma_addr_t address, start;
 	unsigned int pages;
+	unsigned long align_mask = 0;
 	int i;
 
 	pages = iommu_num_pages(paddr, size);
 	paddr &= PAGE_MASK;
 
-	address = dma_ops_alloc_addresses(dev, dma_dom, pages);
+	if (align)
+		align_mask = (1UL << get_order(size)) - 1;
+
+	address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask);
 	if (unlikely(address == bad_dma_address))
 		goto out;
 
@@ -872,7 +878,7 @@ static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
 		return (dma_addr_t)paddr;
 
 	spin_lock_irqsave(&domain->lock, flags);
-	addr = __map_single(dev, iommu, domain->priv, paddr, size, dir);
+	addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false);
 	if (addr == bad_dma_address)
 		goto out;
 
@@ -959,7 +965,7 @@ static int map_sg(struct device *dev, struct scatterlist *sglist,
 		paddr = sg_phys(s);
 
 		s->dma_address = __map_single(dev, iommu, domain->priv,
-					      paddr, s->length, dir);
+					      paddr, s->length, dir, false);
 
 		if (s->dma_address) {
 			s->dma_length = s->length;
@@ -1053,7 +1059,7 @@ static void *alloc_coherent(struct device *dev, size_t size,
 	spin_lock_irqsave(&domain->lock, flags);
 
 	*dma_addr = __map_single(dev, iommu, domain->priv, paddr,
-				 size, DMA_BIDIRECTIONAL);
+				 size, DMA_BIDIRECTIONAL, true);
 
 	if (*dma_addr == bad_dma_address) {
 		free_pages((unsigned long)virt_addr, get_order(size));
-- 
1.5.6.4


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Messages in current thread:
[PATCH 0/23] AMD IOMMU 2.6.28 updates for review, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 05/23] AMD IOMMU: align alloc_coherent addresses pr ..., Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 06/23] AMD IOMMU: add event buffer allocation, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 08/23] AMD IOMMU: save pci_dev instead of devid, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 09/23] AMD IOMMU: add MSI interrupt support, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 10/23] AMD IOMMU: add event handling code, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 11/23] AMD IOMMU: enable event logging, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 13/23] AMD IOMMU: add dma_supported callback, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 18/23] AMD IOMMU: simplify dma_mask_to_pages, Joerg Roedel, (Wed Sep 17, 9:52 am)
[PATCH 23/23] add AMD IOMMU tree to MAINTAINERS file, Joerg Roedel, (Wed Sep 17, 9:52 am)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, FUJITA Tomonori, (Wed Sep 17, 12:20 pm)
Re: [PATCH 18/23] AMD IOMMU: simplify dma_mask_to_pages, FUJITA Tomonori, (Wed Sep 17, 12:20 pm)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, FUJITA Tomonori, (Wed Sep 17, 6:29 pm)
Re: [PATCH 18/23] AMD IOMMU: simplify dma_mask_to_pages, Joerg Roedel, (Thu Sep 18, 12:32 am)
Re: [PATCH 18/23] AMD IOMMU: simplify dma_mask_to_pages, FUJITA Tomonori, (Thu Sep 18, 8:57 am)
Re: [PATCH 18/23] AMD IOMMU: simplify dma_mask_to_pages, Joerg Roedel, (Thu Sep 18, 9:39 am)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, FUJITA Tomonori, (Thu Sep 18, 4:10 pm)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, FUJITA Tomonori, (Fri Sep 19, 3:21 am)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, FUJITA Tomonori, (Fri Sep 19, 11:40 am)
RE: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, Keshavamurthy, Anil S, (Fri Sep 19, 11:47 am)
Re: [PATCH 03/23] AMD IOMMU: implement lazy IO/TLB flushing, Muli Ben-Yehuda, (Sat Sep 20, 10:27 pm)