On Fri, Aug 22, 2008 at 11:43 AM, Jamie Lokier <jamie@shareable.org> wrote:I am only familiar with the Numonyx product line up. If you are using a GL, you'll probably find our P33 a good fit and at competitive prices to GL as I understand it. That's I think 50Mhz. M18 is 100Mhz maybe a little higher. And we just announced our LPDDR 266 part, Velocity LP. A good way of making a rough estimate of read performance is to measure a cache miss latency and convert that to bandwidth. It's usually fairly close. 32Byte cache size / 16 bit bus = 16 word transfers memory controller latency (time from Load instruction to bus activity) = ~300ns (upto 450ns for some processors) initial latency (time to read first word) = ~100ns (60ns - 120ns) clock frequency (time between words) = 50Mhz = 20ns per word bus clean up = ~50ns 32Bytes = 300ns + 100ns + (16 - 1) * 20ns + 50ns = 750ns = 32B/750ns = 40MB/s This is a very simple model and reality is much more nuanced. You also need to check my assume numbers with the reality of your system. Also this doesn't take copying the data to RAM into account which is usually what you are really measuring. That's easy to model though. A rule of thumb is to say that copying to RAM will reduce this value less than 50% because RAM should be at least a little faster than NOR. Nevertheless, If you can't use a simple calculation like this to explain the numbers then you have a poorly configured bus timings or have your cache off. Cache is important because it would make the equation look like this, or worse. 4Bytes = 300ns + 100ns + 1 * 20ns + 50ns = 470ns =4B/470ns =8MB/s For a PXA270 if you go with the defaults it can look like this. 2Bytes = 300ns + 250ns + 250ns = 800ns = 2MB/s So, If you are only getting 0.6MB/s out of your NOR..... You're using it wrong. --
| Tarkan Erimer | Re: Dual-Licensing Linux Kernel with GPL V2 and GPL V3 |
| Greg KH | [GIT PATCH] driver core patches against 2.6.24 |
| Ingo Molnar | [git pull] x86 arch updates for v2.6.25 |
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| Gerrit Renker | [PATCH 16/37] dccp: API to query the current TX/RX CCID |
| Andrew Morton | Re: [BUG] New Kernel Bugs |
